View source for Cyrix 6x86

==Architecture==
[[Image:Cyrix 6x86 arch.svg|250px|thumb|A simplistic block diagram of the Cyrix 6x86 [[microarchitecture]] ]]

The 6x86 is [[superscalar]] and [[superpipelined]] and performs [[register renaming]], [[speculative execution]], [[out-of-order execution]], and [[data dependency]] removal.<ref name="M1DataSheet">{{cite web |title=Cyrix M1 datasheet |url=http://datasheets.chipdb.org/Cyrix/M1/6x86/M1-1.PDF |publisher=Cyrix}}</ref> However, it continued to use native [[x86]] execution and ordinary [[microcode]] only, unlike competitors [[Intel]] and [[AMD]] which introduced the method of dynamic translation to [[micro-operation]]s with [[Pentium Pro]] and [[AMD K5|K5]]. The 6x86 is [[CPU socket|socket]]-compatible with the Intel [[P5 (microarchitecture)#P54C|P54C]] [[Pentium (brand)|Pentium]], and was offered in six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+. These performance levels do not map to the clock speed of the chip itself (for example, a PR 133+ ran at 110&nbsp;MHz, a PR 166+ ran at 133&nbsp;MHz, etc.).<ref>{{FOLDOC|Cyrix+6x86}}</ref>

With regard to internal caches, it has a 16-[[Kibibyte|KB]] primary [[CPU cache|cache]] and a fully associative 256-byte instruction line cache is included alongside the primary cache, which functions as the primary instruction cache.<ref name=M1DataSheet />

The 6x86 and 6x86L were not completely compatible with the Intel [[P5 (microarchitecture)|P5]] [[Pentium (brand)|Pentium]] [[instruction set]] and are not [[multi-processor]] capable. For this reason, the chip identified itself as an [[Intel 80486|80486]] and disabled the [[CPUID]] instruction by default. CPUID support could be enabled by first enabling extended [[condition code register|CCR]] registers then setting bit 7 in CCR4. The lack of full P5 Pentium compatibility caused problems with some applications because programmers had begun to use P5 Pentium-specific instructions. Some companies released patches for their products to make them function on the 6x86.

Compatibility with the Pentium was improved in the 6x86MX, by adding a [[Time Stamp Counter]] to support the P5 Pentium's RDTSC instruction.<ref name=6x86MXDataSheet>{{cite web |url=http://datasheets.chipdb.org/IBM/x86/6x86MX/mx_full.pdf |archive-url=https://web.archive.org/web/20140130164701/http://datasheets.chipdb.org/IBM/x86/6x86MX/mx_full.pdf |archive-date=2014-01-30 |url-status=live |title=IBM 6x86MX datasheet}}</ref> Support for the Pentium Pro's CMOVcc instructions were also added.<ref name=6x86MXDataSheet />