View source for NS32000

==Architecture==
{| class="infobox" style="font-size:88%;width:37em;"
|-
|+ NS 32000 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:left;"| <sup>3</sup><sub>1</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:right;"| <sup>2</sup><sub>3</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="10" | '''General registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R0
| style="background:white; color:black;"| '''R'''egister 0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R1
| style="background:white; color:black;"| '''R'''egister 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R2
| style="background:white; color:black;"| '''R'''egister 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R3
| style="background:white; color:black;"| '''R'''egister 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R4
| style="background:white; color:black;"| '''R'''egister 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R5
| style="background:white; color:black;"| '''R'''egister 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R6
| style="background:white; color:black;"| '''R'''egister 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R7
| style="background:white; color:black;"| '''R'''egister 7
|-
|colspan="10" | '''Index registers'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| 0000 0000
| style="text-align:center;padding-right:21%" colspan="6"| SP1
| style="background:white; color:black;"| '''S'''tack '''P'''ointer (user)
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| 0000 0000
| style="text-align:center;padding-right:21%" colspan="6"| SP0
| style="background:white; color:black;"| '''S'''tack '''P'''ointer (int)
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| 0000 0000
| style="text-align:center;padding-right:21%" colspan="6"| SB
| style="background:white; color:black;"| '''S'''tatic '''B'''ase
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| 0000 0000
| style="text-align:center;padding-right:21%" colspan="6"| FP
| style="background:white; color:black;"| '''F'''rame '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| 0000 0000
| style="text-align:center;padding-right:21%" colspan="6"| INTBASE
| style="background:white; color:black;"| '''Int'''errupt '''Base'''
|-
|colspan="10" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| 0000 0000
| style="text-align:center;padding-right:21%" colspan="6"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|- style="background:silver;color:black"
| style="background-color:white" colspan="4"| &nbsp;
| style="text-align:left" colspan="5"| MOD
| style="background:white; color:black;"| '''Mod'''ule descriptor
|}
{| style="font-size:88%"
|-
|colspan="18" | '''Program Status Register'''
|-
| style="width:60px; text-align:center"| &nbsp;
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver;color:black"
| style="background-color:white"| &nbsp;
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| [[Interrupt flag|I]]
| style="text-align:center"| P
| style="text-align:center"| S
| style="text-align:center"| U
| style="text-align:center"| N
| style="text-align:center"| [[Zero flag|Z]]
| style="text-align:center"| [[Overflow flag|F]]
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| L
| style="text-align:center"| T
| style="text-align:center"| [[Carry flag|C]]
| style="background:white; color:black" | '''PSR'''
|}
|}

The processors have 8 general-purpose 32-bit registers, plus a series of special-purpose registers:
* Frame pointer
* Stack pointer (one each for user and supervisor modes)
* Static base register, for referencing global variables
* Link base register for dynamically linked modules (object orientation)
* Program counter
* A typical processor status register, with a low-order user byte and a high-order system byte.
(Additional system registers not listed).

The instruction set is very much in the [[complex instruction set computer|CISC]] model, with 2-operand instructions, memory-to-memory operations, flexible [[addressing mode]]s, and variable-length byte-aligned instruction encoding.  Addressing modes can involve up to two displacements and two memory indirections per operand as well as scaled indexing, making the longest conceivable instruction 23 bytes. The actual number of instructions is much lower than that of contemporary RISC processors.

Unlike some other processors, automatic increment of the base register is not provided; the only exception is a "top of stack" addressing modes that pop sources and push destinations.  Uniquely, the size of the displacement is encoded in its most significant bits: 0, 10 and 11 preceded 7-, 14- and 30-bit signed displacements.  (Although the processors are otherwise consistently little-endian, displacements in the instruction stream are stored in big-endian order).

General-purpose operands are specified using a 5-bit field. To this can be added an index byte (specifying the index register and 5-bit base address), and up to 2 variable-length displacements per operand.