View source for AltiVec

{{short description|SIMD instruction set extension for the PowerPC ISA}}
{{POWER, PowerPC, and Power ISA}}
'''AltiVec''' is a single-precision [[floating-point]] and integer [[SIMD]] [[instruction set]] designed and owned by [[Apple Inc.|Apple]], [[IBM]], and [[Freescale Semiconductor]] (formerly [[Motorola]]'s Semiconductor Products Sector) &mdash; the [[AIM alliance]].  It is implemented on versions of the [[PowerPC]] processor architecture, including Motorola's [[PowerPC G4|G4]], [[IBM]]'s [[PowerPC 970|G5]] and [[POWER6]] processors, and [[P.A.&nbsp;Semi]]'s [[PWRficient]] PA6T.  AltiVec is a [[trademark]] owned solely by Freescale, so the system is also referred to as '''Velocity Engine''' by Apple and '''VMX''' ('''Vector Multimedia Extension''') by IBM and P.A.&nbsp;Semi.

While AltiVec refers to an instruction set, the implementations in CPUs produced by IBM and Motorola are separate in terms of logic design. To date, no IBM core has included an AltiVec logic design licensed from Motorola or vice versa.

AltiVec is a standard part of the [[Power ISA#Power ISA v.2.03|Power ISA v.2.03]]<ref name="isa203">{{cite web
 |title         = Power ISA v.2.03
 |publisher    = Power.org
 |url          = http://www.power.org/resources/downloads/PowerISA_203_Final_Public.pdf
 |access-date  = 2024-08-09
 |archive-date = 2011-07-27
 |archive-url  = https://web.archive.org/web/20110727183430/http://www.power.org/resources/downloads/PowerISA_203_Final_Public.pdf
 |url-status   = dead
 }}</ref> specification. It was never formally a part of the PowerPC architecture until this specification, although it used [[PowerPC]] instruction formats and syntax and occupied the [[opcode]] space expressly allocated for such purposes.

==Comparison to x86-64 SSE ==

Both VMX/AltiVec and [[Streaming SIMD Extensions|SSE]] feature 128-bit vector registers that can represent sixteen 8-bit [[C data types#Main types|signed or unsigned chars]], eight 16-bit signed or unsigned shorts, four 32-bit ints or four [[IEEE floating-point standard|32-bit]] floating-point variables. Both provide [[CPU cache|cache]]-control instructions intended to minimize [[cache pollution]] when working on streams of data.

They also exhibit important differences. Unlike [[SSE2]], VMX/AltiVec supports a special [[RGB color model|RGB]] "[[pixel]]" data type, but it does not operate on 64-bit double-precision floats, and there is no way to move data directly between scalar and [[vector processor|vector]] registers. In keeping with the "load/store" model of the PowerPC's [[RISC]] design, the vector registers, like the scalar registers, can only be loaded from and stored to memory. However, VMX/AltiVec provides a much more complete set of "horizontal" operations that work across all the elements of a vector; the allowable combinations of data type and operations are much more complete. Thirty-two 128-bit vector registers are provided, compared to eight for SSE and SSE2 (extended to 16 in [[x86-64]]), and most VMX/AltiVec instructions take three register operands compared to only two register/register or register/memory operands on [[IA-32]].

VMX/AltiVec is also unique in its support for a flexible vector permute instruction, in which each byte of a resulting vector value can be taken from any byte of either of two other vectors, parametrized by yet another vector. This allows for sophisticated manipulations in a single instruction.

Recent versions{{when|date=October 2020}} of the [[GNU Compiler Collection]] (GCC), [[IBM VisualAge]] compiler and other compilers provide [[intrinsic function|intrinsics]] to access VMX/AltiVec instructions directly from [[C (programming language)|C]] and [[C++]] programs. As of version&nbsp;4, the GCC also includes [[Automatic vectorization|auto-vectorization]] capabilities that attempt to intelligently create VMX/Altivec-accelerated binaries without the need for the programmer to use intrinsics directly. The "vector" type keyword is introduced to permit the declaration of native vector types, e.g., <code>vector unsigned char foo;</code> declares a 128-bit vector variable named "foo" containing sixteen 8-bit unsigned chars. The full complement of arithmetic and binary operators is defined on vector types so that the normal C expression language can be used to manipulate vector variables. There are also overloaded intrinsic functions such as <code>vec_add</code> that emit the appropriate [[opcode]] based on the type of the elements within the vector, and very strong type checking is enforced. In contrast, the Intel-defined data types for IA-32 SIMD registers declare only the size of the vector register (128 or 64 bits) and in the case of a 128-bit register, whether it contains integers or floating-point values. The programmer must select the appropriate intrinsic for the data types in use, e.g., <code>_mm_add_epi16(x,&nbsp;y)</code> for adding two vectors containing eight 16-bit integers.

==Development history==
The Power Vector Media Extension (VMX) was developed between 1996 and 1998 by a collaborative project between Apple, IBM, and Motorola. 
Apple was the primary customer for Power Vector Media Extension (VMX) until Apple switched to Intel-made, x86-based CPUs on June 6, 2005. They used it to accelerate [[multimedia]] applications such as [[QuickTime]], [[iTunes]] and key parts of Apple's [[Mac OS X]] including in the [[Quartz (graphics layer)|Quartz graphics compositor]].  Other companies such as Adobe used AltiVec to optimize their image-processing programs such as [[Adobe Photoshop]]. Motorola was the first to supply AltiVec enabled processors starting with their G4 line.  AltiVec was also used in some embedded systems for high-performance digital signal processing.

IBM consistently left VMX out of their earlier [[IBM Power microprocessors|POWER microprocessors]], which were intended for server applications where it was not very useful. The [[POWER6]] microprocessor, introduced in 2007, implements AltiVec. The last desktop microprocessor from IBM, the [[PowerPC 970]] (dubbed the "G5" by Apple) also implemented AltiVec with hardware similar to that of the [[PowerPC G4|PowerPC 7400]].

AltiVec is a brandname trademarked by Freescale (previously Motorola) for the standard ''Category:Vector'' part of the [[Power ISA#Power ISA v.2.03|Power ISA v.2.03]]<ref name="isa203" /> specification.  This category is also known as VMX (used by IBM), and "Velocity Engine" (a brand name previously used by Apple).

The [[Cell microprocessor|Cell]] Broadband Engine, used in (amongst other things) the [[PlayStation 3]], also supports Power Vector Media Extension (VMX) in its PPU, with the SPU ISA being enhanced but architecturally similar.

Freescale is bringing an enhanced version of AltiVec to [[PowerPC e6500|e6500]] based [[QorIQ]] processors.

=== VMX128 ===
IBM enhanced VMX for use in [[Xenon (processor)|Xenon]] (Xbox 360) and called this enhancement VMX128. The enhancements comprise new routines targeted at gaming (accelerating 3D graphics and game physics)<ref>{{cite web
 |title=The Microsoft Xbox 360 CPU story 
 |publisher=IBM
 |url=http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign 
 |url-status=bot: unknown 
 |archive-url=https://web.archive.org/web/20080120000613/http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign 
 |archive-date=2008-01-20 
|date=October 2015
 }}</ref> and a total of 128 registers. VMX128 is not entirely compatible with VMX/Altivec, as a number of integer operations were removed to make space for the larger register file and additional application-specific operations.<ref>[https://web.archive.org/web/20120208052530/http://domino.research.ibm.com/comm/research.nsf/pages/r.arch.simd.html Using data-parallel SIMD architecture in video games and supercomputers] IBM Research</ref><ref>[https://patents.google.com/patent/US7421566  Implementing instruction set architectures with non-contiguous register file specifiers]  US Patent 7,421,566</ref>

=== VSX (Vector Scalar Extension) ===
[[Power ISA#Power ISA v.2.06|Power ISA v2.06]] introduced VSX vector-scalar instructions<ref name="vsx">{{cite web
	|title=Workload acceleration with the IBM POWER vector-scalar architecture
	|publisher=IBM
	|date=2016-03-01
	|url=https://www.researchgate.net/publication/299472451
	|access-date=2017-05-02
	|archive-date=2022-01-25
	|archive-url=https://web.archive.org/web/20220125060920/https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture
	|url-status=live
	}}</ref> which extend SIMD processing for the Power ISA to support up to 64 registers, with support for regular floating point, decimal floating point and vector execution. [[POWER7]] is the first Power ISA processor to implement Power ISA v2.06.

New instructions are introduced by IBM under the Vector Media Extension category for integer operations as part of the VSX extension in Power ISA 2.07.

New integer vector instructions were introduced by IBM following the VMX encodings as part of the VSX extension in  Power ISA v3.0. Shall be introduced with [[POWER9]] processors.<ref>{{Cite web | url=https://sourceware.org/ml/binutils/2015-11/msg00071.html | title=Peter Bergner - &#91;PATCH, COMMITTED&#93; Add full Power ISA 3.0 / POWER9 binutils support | access-date=2016-12-24 | archive-date=2016-03-07 | archive-url=https://web.archive.org/web/20160307013258/https://sourceware.org/ml/binutils/2015-11/msg00071.html | url-status=live }}</ref>

== Issues ==
In C++, the standard way of accessing AltiVec support is mutually exclusive with the use of the Standard Template Library <code>vector<></code> class template due to the treatment of "vector" as a reserved word when the compiler does not implement the context-sensitive keyword version of vector.  However, it may be possible to combine them using compiler-specific workarounds; for instance, in GCC one may do <code>#undef vector</code> to remove the <code>vector</code> keyword, and then use the GCC-specific <code>__vector</code> keyword in its place.

AltiVec prior to Power ISA 2.06 with VSX lacks loading from memory using a type's natural alignment. For example, the code below requires special handling for Power6 and below when the effective address is not 16-byte aligned. The special handling adds 3 additional instructions to a load operation when VSX is not available.
<syntaxhighlight lang="C" line='line'>#include <altivec.h>
typedef __vector unsigned char uint8x16_p;
typedef __vector unsigned  int uint32x4_p;
...
int main(int argc, char* argv)
{
    /* Natural alignment of vals is 4; and not 16 as required */
    unsigned int vals[4] = { 1, 2, 3, 4 };
    uint32x4_p vec;

#if defined(__VSX__) || defined(_ARCH_PWR8)
    vec = vec_xl(0, vals);
#else
    const uint8x16_p perm = vec_lvsl(0, vals);
    const uint8x16_p low  = vec_ld(0, vals);
    const uint8x16_p high = vec_ld(15, vals);
    vec = (uint32x4_p)vec_perm(low, high, perm);
#endif

}</syntaxhighlight>

AltiVec prior to Power ISA 2.06 with VMX lacks 64-bit integer support. Developers who wish to operate on 64-bit data will develop routines from 32-bit components. For example, below are examples of 64-bit <code>add</code> and <code>subtract</code> in C using a vector with four 32-bit words on a [[Endianness|big-endian machine]]. The permutes move the carry and borrow bits from columns 1 and 3 to columns 0 and 2 like in school-book math. A little-endian machine would need a different mask.

<syntaxhighlight lang="C" line='line'>#include <altivec.h>
typedef __vector unsigned char uint8x16_p;
typedef __vector unsigned  int uint32x4_p;
...

/* Performs a+b as if the vector held two 64-bit double words */
uint32x4_p add64(const uint32x4_p a, const uint32x4_p b)
{
    const uint8x16_p cmask = {4,5,6,7, 16,16,16,16, 12,13,14,15, 16,16,16,16};
    const uint32x4_p zero = {0, 0, 0, 0};

    uint32x4_p cy = vec_addc(vec1, vec2);
    cy = vec_perm(cy, zero, cmask);
    return vec_add(vec_add(vec1, vec2), cy);
}

/* Performs a-b as if the vector held two 64-bit double words */
uint32x4_p sub64(const uint32x4_p a, const uint32x4_p b)
{
    const uint8x16_p bmask = {4,5,6,7, 16,16,16,16, 12,13,14,15, 16,16,16,16};
    const uint32x4_p amask = {1, 1, 1, 1};
    const uint32x4_p zero = {0, 0, 0, 0};

    uint32x4_p bw = vec_subc(vec1, vec2);
    bw = vec_andc(amask, bw);
    bw = vec_perm(bw, zero, bmask);
    return vec_sub(vec_sub(vec1, vec2), bw);
}</syntaxhighlight>

Power ISA 2.07 used in Power8 finally provided the 64-bit double words. A developer working with Power8 needs only to perform the following.

<syntaxhighlight lang="C" line='line'>#include <altivec.h>
typedef __vector unsigned long long uint64x2_p;
...

/* Performs a+b using native vector 64-bit double words */
uint64x2_p add64(const uint64x2_p a, const uint64x2_p b)
{
    return vec_add(a, b);
}

/* Performs a-b using native vector 64-bit double words */
uint64x2_p sub64(const uint64x2_p a, const uint64x2_p b)
{
    return vec_sub(a, b);
}</syntaxhighlight>

== Implementations ==
The following processors have AltiVec, VMX or VMX128 included

===Motorola/Freescale===
{{columns-list |colwidth=30em|
*[[PowerPC G4#PowerPC 7400|MPC7400]]
*[[PowerPC G4#PowerPC 7410|MPC7410]]
*[[PowerPC G4#PowerPC 7450|MPC7450]]
*[[PowerPC G4#PowerPC 7445 and 7455|MPC7445/7455]]
*[[PowerPC G4#PowerPC 7447 and 7457|MPC7447/7447A/7457]]
*[[PowerPC e600#MPC7448|MPC7448]]
*[[PowerPC e600#MPC864x|MPC8641/8641D]]
*[[PowerPC e600#MPC864x|MPC8640/8640D]]
*[[PowerPC e600#MPC8610|MPC8610]]
*[[PowerPC e6500|T2081/T2080]]
*[[PowerPC e6500|T4080/T4160/T4240]]
*[[PowerPC e6500|B4420/B4860]]
}}

===IBM===
{{columns-list |colwidth=30em|
*[[PowerPC 970]]
*[[PowerPC 970#PowerPC 970FX|PowerPC 970FX]]
*[[PowerPC 970#PowerPC 970MP|PowerPC 970MP]]
*[[Xenon (processor)|Xenon]]
*[[Cell (microprocessor)|Cell B.E.]]
*[[Cell (microprocessor)#PowerXCell 8i|PowerXCell 8i]]
*[[POWER6|POWER6/POWER6+]]
*[[POWER7|POWER7/POWER7+]]
*[[POWER8]]
*[[POWER9]]
*[[Power10]]
}}

===P.A. Semi===
*[[PWRficient|PA6T]]

== Software applications ==
The following software applications are known to leverage AltiVec or VMX hardware acceleration.

* Helios has a native POWER9 / POWER10 port with support for VMX.<ref>{{Cite web|title=FAQ, Helios|url=https://heliosmusic.io/faq/|access-date=2021-07-09|website=Helios|language=en-US}}</ref>

== References ==
{{Reflist}}

== External links ==
*[https://web.archive.org/web/20120910081558/http://www.ibm.com/developerworks/library/pa-unrollav1/ Unrolling AltiVec, Part 1: Introducing the PowerPC SIMD unit] at IBM; archived at the [[Wayback Machine]] on 2012-09-10
*[https://web.archive.org/web/20120204044643/http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCALTVC AltiVec Technologies] at Freescale; archived at the [[Wayback Machine]] on 2012-02-04
*[https://web.archive.org/web/20120208052530/http://domino.research.ibm.com/comm/research.nsf/pages/r.arch.simd.html Using data-parallel SIMD architecture in video games and supercomputers] at IBM; archived at the [[Wayback Machine]] on 2012-02-08
*[https://web.archive.org/web/20091128121821/http://developer.apple.com/hardwaredrivers/ve/index.html Velocity Engine] at Apple; archived at the [[Wayback Machine]] on 2009-11-28
*[http://noisymime.org/blogimages/SIMD.pdf SIMD history and performance comparison]

{{Multimedia extensions}}

[[Category:SIMD computing]]
[[Category:Cell BE architecture]]
[[Category:Power microprocessors]]
[[Category:Instruction set extensions]]