View source for IA-64

{{Short description|Microprocessor instruction set architecture}}
{{Distinguish|text=[[x86-64]], AMD's 64-bit extension of the IA-32 ISA}}
{{infobox CPU architecture
| name       = Intel Itanium architecture
| designer   = [[Hewlett-Packard|HP]] and [[Intel]]
| bits       = 64-bit
| introduced = 2001
| design     = [[Explicitly parallel instruction computing|EPIC]]
| type       = [[Load–store]]
| encoding   = Fixed
| branching  = Condition register
| endianness = Selectable
| gpr        = 128 (64 bits plus 1 [[speculative execution|trap bit]]; 32 are static, 96 use [[register window]]s); 64 1-bit predicate registers
| fpr        = 128
}}

'''IA-64''' ('''Intel Itanium architecture''') is the [[instruction set architecture]] (ISA) of the discontinued [[Itanium]] family of 64-bit [[Intel]] [[microprocessor]]s. The basic ISA specification originated at [[Hewlett-Packard]] (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, [[List of Intel codenames|codenamed]] ''Merced'', was released in 2001.

The Itanium architecture is based on explicit [[instruction-level parallelism]], in which the [[compiler]] decides which instructions to execute in parallel. This contrasts with [[superscalar]] architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including ''[[Tukwila (processor)|Tukwila]]'', cores execute up to six [[instructions per cycle]].

In 2008, Itanium was the fourth-most deployed microprocessor architecture for [[enterprise information system|enterprise-class systems]], behind [[x86-64]], [[Power ISA]], and [[SPARC]].<ref name="ITJungle">{{cite web | url = https://www.itjungle.com/tlb/tlb052708-story03.html | title = The Server Biz Enjoys the X64 Upgrade Cycle in Q1 | access-date = 2008-10-29 | last = Morgan | first = Timothy | date = 2008-05-27 | work = IT Jungle | archive-date = 2016-03-03 | archive-url = https://web.archive.org/web/20160303203839/http://www.itjungle.com/tlb/tlb052708-story03.html | url-status = live }}</ref>

In 2019, Intel announced the discontinuation of the last supported CPUs for the IA-64 architecture. [[Microsoft Windows]] versions from Server 2003<ref>{{cite web | title=Windows Server 2003 - BetaWiki | url=https://betawiki.net/wiki/Windows_Server_2003 }}</ref> to Server 2008 R2<ref>https://betawiki.net/wiki/Windows_Server_2008_R2</ref> supported IA-64; later versions did not support it. The [[Linux kernel]] supported it for much longer but dropped support by version 6.7 in 2024 (while still supported in Linux 6.6 [[long-term support|LTS]]). Only a few other operating systems, such as [[HP-UX]], [[OpenVMS]], and [[FreeBSD]], ever supported IA-64; HP-UX's support ended in December 2025; OpenVMS still supports it, but FreeBSD discontinued support in FreeBSD 11.

== History ==
[[File:Itanium architecture.svg|thumb|The Intel Itanium architecture]]

=== Development ===

In 1989, HP began to become concerned that [[reduced instruction set computing]] (RISC) architectures were approaching a processing limit at one [[instruction per cycle]]. Both Intel and HP researchers had been exploring computer architecture options for future designs and separately began investigating a new concept known as [[very long instruction word]] (VLIW)<ref name="HP_Labs">{{cite web|url=http://www.hpl.hp.com/news/2001/apr-jun/itanium.html|title=Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture|date=June 2001|access-date=2007-03-23|work=[[Hewlett-Packard|HP]] Labs|archive-date=2012-03-04|archive-url=https://web.archive.org/web/20120304045612/http://www.hpl.hp.com/news/2001/apr-jun/itanium.html|url-status=dead}}</ref> which came out of research by [[Yale University]] in the early 1980s.<ref>{{cite conference | first = Joseph A. | last = Fisher | author-link = Josh Fisher | year = 1983 | title = Very Long Instruction Word architectures and the ELI-512 | conference = International Symposium on Computer Architecture | book-title = Proceedings of the 10th annual international symposium on Computer architecture | publisher = [[Association for Computing Machinery]] (ACM) | location = New York, NY, USA | pages = 140–150 | doi = 10.1145/800046.801649 | isbn = 0-89791-101-6| doi-access= free }}</ref>

VLIW is a computer architecture concept (like RISC and [[complex instruction set computing|CISC]]) where a single instruction word contains multiple instructions encoded in one very long instruction word to facilitate the processor executing multiple [[instruction (computer science)|instructions]] in each clock cycle. Typical VLIW implementations rely heavily on sophisticated compilers to determine at compile time which instructions can be executed at the same time and the proper scheduling of these instructions for execution and also to help predict the direction of branch operations. The value of this approach is to do more useful work in fewer clock cycles and to simplify processor instruction scheduling and branch prediction hardware requirements, with a penalty in increased processor complexity, cost, and energy consumption in exchange for faster execution.

=== Production ===

During this time, HP had begun to believe that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors. Intel had also been researching several architectural options for going beyond the x86 ISA to address high-end enterprise server and high-performance computing (HPC) requirements.

Intel and HP partnered in 1994 to develop the IA-64 ISA, using a variation of VLIW design concepts which Intel named [[explicitly parallel instruction computing]] (EPIC). Intel's goal was to leverage the expertise HP had developed in their early VLIW work along with their own to develop a volume product line targeted at the aforementioned high-end systems that could be sold to all original equipment manufacturers (OEMs), while HP wished to be able to purchase off-the-shelf processors built using Intel's volume manufacturing and contemporary process technology that were better than their PA-RISC processors.

Intel took the lead on the design and commercialization process, while HP contributed to the ISA definition, the Merced/Itanium microarchitecture, and Itanium 2. The original goal year for delivering the first Itanium family product, Merced, was 1998.<ref name="HP_Labs" />

=== Marketing ===

Intel's product marketing and industry engagement efforts were substantial and achieved design wins with the majority of enterprise server OEMs, including those based on RISC processors at the time. Industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant both RISC and CISC architectures for all general-purpose applications.<ref name="anand">{{cite web | url = https://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598 | title = Itanium–Is there light at the end of the tunnel? | access-date = 2007-03-23 | last = De Gelas | first = Johan | date = 2005-11-09 | work = [[AnandTech]] | archive-date = 2012-05-03 | archive-url = https://web.archive.org/web/20120503094946/http://www.anandtech.com/show/1854 | url-status = dead }}</ref><ref name="Venturebeat">{{cite web | url = https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/ | title = Exit interview: Retiring Intel chairman Craig Barrett on the industry's unfinished business | access-date = 2009-05-17 | last = Takahashi | first = Dean | date = 2009-05-08 | work = VentureBeat | archive-date = 2018-04-21 | archive-url = https://web.archive.org/web/20180421095016/https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/ | url-status = live }}</ref> [[Compaq]] and [[Silicon Graphics]] decided to abandon further development of the [[DEC Alpha|Alpha]] and [[MIPS architecture|MIPS]] architectures respectively in favor of migrating to IA-64.<ref name="cautionary">{{cite web | url = https://news.zdnet.com/2100-9584-5984747.html | title = Itanium: A cautionary tale | access-date = 2007-11-01 | date = 2005-12-07 | work = Tech News on ZDNet | archive-url = https://web.archive.org/web/20080209211056/http://news.zdnet.com/2100-9584-5984747.html | archive-date = 2008-02-09}}</ref>

By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Itanium began slipping.<ref name="geek1">{{cite web | url = https://news.cnet.com/2100-1001-228204.html | title = Intel's Merced chip may slip further | last = Shankland | first = Stephen | access-date = 2008-10-16 | date = 1999-07-08 | work = CNET News | archive-date = 2012-10-24 | archive-url = https://web.archive.org/web/20121024072154/http://news.cnet.com/2100-1001-228204.html | url-status = live }}</ref> Since Itanium was the first ever EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depended on compiler capabilities that had never been implemented before, so more research was needed.<ref name="Research">{{cite web | url = https://cs.nyu.edu/courses/spring02/V22.0480-002/vliw.pdf | title = Microprocessors&nbsp;— VLIW, The Past | access-date = 2018-06-26 | date = 2002-04-18 | work = NY University | archive-date = 2018-06-27 | archive-url = https://web.archive.org/web/20180627202317/https://cs.nyu.edu/courses/spring02/V22.0480-002/vliw.pdf | url-status = live }}</ref>

Several groups developed operating systems for the architecture, including [[Microsoft Windows]], [[Unix]] and [[Unix-like]] systems such as [[Linux]], [[HP-UX]], [[FreeBSD]], [[Solaris (operating system)|Solaris]],<ref name="Solaris-Merced1">{{cite web | url = https://www.computerworld.com/home/news.nsf/all/9909013sunsol | title = Solaris for IA-64 coming this fall | last = Vijayan | first = Jaikumar | date = 1999-09-01 | website = [[Computerworld]] | archive-date = 2000-01-15 | archive-url = https://web.archive.org/web/20000115084746/http://www.computerworld.com/home/news.nsf/all/9909013sunsol | url-status = dead }}</ref><ref name="Solaris-Merced2">{{cite web | url = https://www.eetimes.com/core-logic-efforts-under-way-for-merced/ | title = Core-logic efforts under way for Merced | last = Wolfe | first = Alexander | access-date = October 26, 2025 | date = 1999-09-02 | work = EE Times}}</ref><ref name="Solaris-Merced3">{{cite web | url = http://findarticles.com/p/articles/mi_m0EIN/is_1998_March_10/ai_20369933 | archive-url = https://web.archive.org/web/20040920130611/http://www.findarticles.com/p/articles/mi_m0EIN/is_1998_March_10/ai_20369933 | url-status = dead | archive-date = 2004-09-20 | title = Sun Introduces Solaris Developer Kit for Intel to Speed Development of Applications On Solaris; Award-winning Sun Tools Help ISVs Easily Develop for Solaris on Intel Today | access-date = 2008-10-16 | date = 1998-03-10 | work = Business Wire}}</ref> [[Tru64 UNIX]],<ref name="cautionary" /> and [[Monterey/64]]<ref>{{cite web | url = http://www.news.com/2100-1001-229335.html | title = Next-generation chip passes key milestone | access-date = 2007-11-01 | date = 1999-09-17 | work = CNET News.com | archive-url = https://web.archive.org/web/20110809204935/http://news.cnet.com/2100-1001-229335.html | archive-date = 2011-08-09 }}</ref> (the last three were canceled before reaching the market). In 1999, Intel led the formation of an open-source industry consortium to port Linux to IA-64 they named "Trillium" (and later renamed "Trillian" due to a trademark issue), which was led by Intel and included [[Caldera Systems]], [[CERN]], [[Cygnus Solutions]], Hewlett-Packard, IBM, [[Red Hat]], [[Silicon Graphics|SGI]], [[SUSE S.A.|SuSE]], [[TurboLinux]] and [[VA Linux Systems]]. As a result, a working IA-64 Linux was delivered ahead of schedule and was the first OS to run on the new Itanium processors.

Intel announced the official name of the processor, ''Itanium'', on October 4, 1999.<ref>{{cite web | url = http://www.cnet.com/news/intel-names-merced-chip-itanium/ | title = Intel names Merced chip Itanium | access-date = 2007-04-30 | last = Kanellos | first = Michael | date = 1999-10-04 | work = [[CNET]] News.com | archive-date = 2015-12-30 | archive-url = https://web.archive.org/web/20151230133330/http://www.cnet.com/news/intel-names-merced-chip-itanium/ | url-status = live }}</ref> Within hours, the name ''Itanic'' had been coined on a [[Usenet]] newsgroup as a [[pun]] on the name [[RMS Titanic|''Titanic'']], the "unsinkable" [[ocean liner]] that sank on its maiden voyage in 1912.<ref>{{cite newsgroup | url = https://groups.google.com/d/msg/comp.sys.mac.advocacy/UiOOaXF3-lI/f3nje9CHPx0J | title = Re:Itanium | access-date = 2013-12-19 | last = Finstad | first = Kraig | date = 1999-10-04 | newsgroup= comp.sys.mac.advocacy}}</ref>

The very next day on 5th October 1999, AMD announced their plans to extend Intel's x86 instruction set to include a fully downward compatible 64-bit mode, additionally revealing AMD's newly coming x86 64-bit architecture, which the company had already worked on, to be incorporated into AMD's upcoming eighth-generation microprocessor, code-named [[Opteron|''SledgeHammer'']].<ref name="AMD64-announcement">{{cite press release | title = AMD Discloses New Technologies At Microporcessor Forum | publisher = AMD | date = October 5, 1999 | url = https://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx | archive-url = https://web.archive.org/web/20120308030806/http://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx | archive-date = March 8, 2012 | access-date= August 15, 2022 }}</ref> AMD also signaled a full disclosure of the architecture's specifications and further details to be available in August 2000.<ref name="AMD-spec-x86-64">{{cite press release | title = AMD Releases x86-64 Architectural Specification; Enables Market Driven Migration to 64-Bit Computing | publisher = AMD | date = August 10, 2000 | url = https://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx | archive-url = https://web.archive.org/web/20120308025559/http://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx | archive-date = March 8, 2012 | access-date= August 15, 2022 }}</ref>

As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, AMD's [[AMD64]] architecture-extension was positioned from the beginning as an evolutionary way to add [[64-bit computing]] capabilities to the existing x86 architecture, while still supporting legacy 32-bit x86 [[machine code|code]], as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64.

=== End of life ===

In January 2019, Intel announced that Kittson would be discontinued, with a last order date of January 2020, and a last ship date of July 2021.<ref name="Anton Shilov">{{cite web|url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums|title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums|author=Anton Shilov|date=January 31, 2019|website=[[AnandTech]]|access-date=April 16, 2019|archive-date=April 16, 2019|archive-url=https://web.archive.org/web/20190416110949/https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums|url-status=dead}}</ref><ref>{{cite web|url=http://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf|title=Product Change Notification|date=January 30, 2019|access-date=May 9, 2019|archive-date=February 1, 2019|archive-url=https://web.archive.org/web/20190201180014/https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf|url-status=live}}</ref> In November 2023, IA-64 support was removed from the [[Linux kernel]] and is since then maintained [[wiktionary:out-of-tree|out-of-tree]].<ref>{{cite news |last1=Larabel |first1=Michael |title=Intel Itanium IA-64 Support Removed With The Linux 6.7 Kernel |url=https://www.phoronix.com/news/Intel-IA-64-Removed-Linux-6.7 |access-date=4 November 2023 |work=www.phoronix.com |publisher=Phoronix |date=2 November 2023 |language=en}}</ref><ref>{{cite web |url=https://github.com/linux-ia64/ |title=linux-ia64 |website=GitHub |quote=Maintenance and development of the Linux operating system for Intel Itanium architecture (IA-64) |access-date=October 1, 2024}}</ref><ref>{{cite web |url=http://epic-linux.org/ |title=EPIC Linux |access-date=October 1, 2024}}</ref>

== Architecture ==

Intel has extensively documented the Itanium [[instruction set]]<ref name="manual">{{cite web|url=https://www.intel.com/content/www/us/en/processors/itanium/itanium-architecture-vol-1-2-3-4-reference-set-manual.html|title=Intel Itanium Architecture Software Developer's Manual|access-date=2019-04-08|archive-date=2019-04-08|archive-url=https://web.archive.org/web/20190408192416/https://www.intel.com/content/www/us/en/processors/itanium/itanium-architecture-vol-1-2-3-4-reference-set-manual.html|url-status=dead}}</ref> and the technical press has provided overviews.<ref name="anand" /><ref name="geek1"/>

The architecture has been renamed several times during its history. HP originally called it ''PA-WideWord''. Intel later called it ''IA-64'', then ''Itanium Processor Architecture'' (IPA),<ref>{{cite web | url = http://www.hpworks.org.uk/newsletter/ping-year-ago.rtf | title = HPWorks Newsletter | access-date = 2008-01-24 | date = September 2001 | url-status = dead | archive-url = https://web.archive.org/web/20081120160309/http://www.hpworks.org.uk/newsletter/ping-year-ago.rtf | archive-date = 2008-11-20 }}</ref> before settling on ''Intel Itanium Architecture'', but it is still widely referred to as ''IA-64''.

It is a 64-bit register-rich explicitly parallel architecture. The base data word is 64 bits, byte-addressable. The [[logical address]] space is 2<sup>64</sup> bytes. The architecture implements [[branch predication|predication]], [[speculative execution|speculation]], and [[branch prediction]]. It uses variable-sized register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.

The architecture implements a large number of registers:<ref>{{cite web |url=https://blogs.msdn.microsoft.com/oldnewthing/20150727-00/?p=90821 |title=The Itanium processor, part 1: Warming up |last=Chen |first=Raymond |date=2015-07-27 |access-date=2018-10-31 |archive-date=2018-11-01 |archive-url=https://web.archive.org/web/20181101015611/https://blogs.msdn.microsoft.com/oldnewthing/20150727-00/?p=90821 |url-status=live }}</ref><ref>{{cite web |url=https://blogs.msdn.microsoft.com/oldnewthing/20150728-00/?p=90811 |title=The Itanium processor, part 2: Instruction encoding, templates, and stops |last=Chen |first=Raymond |date=2015-07-28 |access-date=2018-10-31 |archive-date=2018-11-01 |archive-url=https://web.archive.org/web/20181101015522/https://blogs.msdn.microsoft.com/oldnewthing/20150728-00/?p=90811 |url-status=live }}</ref><ref>{{cite web |url=https://blogs.msdn.microsoft.com/oldnewthing/20150729-00/?p=90801 |title=The Itanium processor, part 3: The Windows calling convention, how parameters are passed |last=Chen |first=Raymond |date=2015-07-29 |access-date=2018-10-31 |archive-date=2018-11-01 |archive-url=https://web.archive.org/web/20181101015652/https://blogs.msdn.microsoft.com/oldnewthing/20150729-00/?p=90801 |url-status=live }}</ref>
* 128 general integer [[processor register|registers]], which are 64-bit plus one trap bit ("NaT", which stands for "not a thing") used for [[speculative execution]]. 32 of these are static, the other 96 are stacked using variably-sized [[register window]]s, or rotating for pipelined loops. <code>gr<sub>0</sub></code> always reads 0.
* 128 [[floating-point]] registers. The floating-point registers are 82 bits long to preserve precision for intermediate results. Instead of a dedicated "NaT" trap bit like the integer registers, floating-point registers have a trap value called "NaTVal" ("Not a Thing Value"), similar to (but distinct from) [[NaN]]. These also have 32 static registers and 96 windowed or rotating registers. <code>fr<sub>0</sub></code> always reads +0.0, and <code>fr<sub>1</sub></code> always reads +1.0.
* 64 one-bit predicate registers. These have 16 static registers and 48 windowed or rotating registers. <code>pr<sub>0</sub></code> always reads 1 (true).
* 8 branch registers, for the addresses of indirect jumps. <code>br<sub>0</sub></code> is set to the return address when a function is called with <code>br.call</code>.
* 128 special purpose (or "application") registers, which are mostly of interest to the kernel and not ordinary applications. For example, one register called <code>bsp</code> points to the second stack, which is where the hardware will automatically spill registers when the register window wraps around.

Each 128-bit instruction word is called a ''bundle'', and contains three ''slots'' each holding a 41-bit [[instruction (computer science)|instruction]], plus a 5-bit ''template'' indicating which type of instruction is in each slot. Those types are M-unit (memory instructions), I-unit (integer ALU, non-ALU integer, or long immediate extended instructions), F-unit (floating-point instructions), or B-unit (branch or long branch extended instructions). The template also encodes ''stops'' which indicate that a data dependency exists between data before and after the stop. All instructions between a pair of stops constitute an ''instruction group'', regardless of their bundling, and must be free of many types of data dependencies; this knowledge allows the processor to execute instructions in parallel without having to perform its own complicated data analysis, since that analysis was already done when the instructions were written.

Within each slot, all but a few instructions are predicated, specifying a predicate register, the value of which (true or false) will determine whether the instruction is executed. Predicated instructions which should always execute are predicated on <code>pr<sub>0</sub></code>, which always reads as true.

The IA-64 assembly language and instruction format was deliberately designed to be written mainly by compilers, not by humans. Instructions must be grouped into bundles of three, ensuring that the three instructions match an allowed template. Instructions must issue stops between certain types of data dependencies, and stops can also only be used in limited places according to the allowed templates.

=== Instruction execution ===

The fetch mechanism can read up to two bundles per clock from the L1 [[CPU cache|cache]] into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the [[instruction set]], and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units.

The execution unit groups include:
* Six general-purpose ALUs, two integer units, one shift unit
* Four data cache units
* Six multimedia units, two parallel shift units, one parallel multiply, one [[Hamming weight|population count]]
* Two 82-bit floating-point [[multiply–accumulate]] units, two [[SIMD]] floating-point multiply–accumulate units (two 32-bit operations each)<ref>Sharangpani, Harsh; Arora, Ken (2000). "Itanium Processor Microarchitecture". ''[[IEEE Micro]]''. pp. 38–39.</ref>
* Three branch units

Ideally, the compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a [[multiply–accumulate operation]], a single floating-point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four [[FLOP]]s per cycle. For example, the 800&nbsp;MHz Itanium had a theoretical rating of 3.2&nbsp;[[GFLOPS]] and the fastest Itanium 2, at 1.67&nbsp;GHz, was rated at 6.67&nbsp;GFLOPS.

In practice, the processor may often be underutilized, with not all slots filled with useful instructions due to e.g. data dependencies or limitations in the available bundle templates. The densest possible code requires 42.6 bits per instruction, compared to 32 bits per instruction on traditional RISC processors of the time, and no-ops due to wasted slots further decrease the density of code. Additional instructions for speculative loads and hints for branches and cache are impractical to generate optimally, because a compiler cannot predict the contents of the different cache levels on a system running multiple processes and taking interrupts.

=== Memory architecture ===

From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16&nbsp;KB of Level 1 instruction cache and 16&nbsp;KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256&nbsp;KB. The Level 3 cache was also unified and varied in size from 1.5&nbsp;MB to 24&nbsp;MB. The 256&nbsp;KB L2 cache contains sufficient logic to handle [[semaphore (programming)|semaphore]] operations without disturbing the main [[arithmetic logic unit]] (ALU).

Main memory is accessed through a [[computer bus|bus]] to an off-chip [[chipset]]. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2×128 bits per clock cycle, so the 200&nbsp;MHz McKinley bus transferred 6.4&nbsp;GB/s, and the 533&nbsp;MHz Montecito bus transfers 17.056&nbsp;GB/s<ref>{{cite web | last = Cataldo | first = Anthony | title = Intel outfits Itanium processor for faster runs | website = [[EE Times]] | date = 2001-08-30 | url = https://www.eetimes.com/intel-outfits-itanium-processor-for-faster-runs/ | access-date = 2020-01-19 | archive-date = 2020-08-01 | archive-url = https://web.archive.org/web/20200801201320/https://www.eetimes.com/intel-outfits-itanium-processor-for-faster-runs/ | url-status = live }}</ref>

=== Architectural changes ===
{{Redirect|Intel VT-i|the x86 virtualization extensions|Intel VT-x}}

Itanium processors released prior to 2006 had hardware support for the [[IA-32]] architecture to permit support for legacy server applications, but performance for IA-32 code was much worse than for native code and also worse than the performance of contemporaneous x86 processors. In 2005, Intel developed the [[IA-32 Execution Layer]] (IA-32 EL), a software emulator that provides better performance. With Montecito, Intel therefore eliminated hardware support for IA-32 code.

In 2006, with the release of [[Montecito (processor)|Montecito]], Intel made a number of enhancements to the basic processor architecture including:<ref>{{cite web|url=http://www.intel.com/products/processor/itanium/index.htm |title=Intel product announcement |access-date=2007-05-16 |work=[[Intel]] web site |url-status=dead |archive-url=https://web.archive.org/web/20071107044019/http://www.intel.com/products/processor/itanium/index.htm |archive-date=November 7, 2007 }}</ref>
* Hardware multithreading: Each processor core maintains context for two threads of execution. When one thread stalls during memory access, the other thread can execute. Intel calls this "coarse multithreading" to distinguish it from the "[[hyper-threading]] technology" Intel integrated into some [[x86]] and [[x86-64]] microprocessors.
* Hardware support for [[hardware-assisted virtualization|virtualization]]: Intel added Intel Virtualization Technology (Intel VT-i), which provides hardware assists for core virtualization functions. Virtualization allows a software "[[hypervisor]]" to run multiple operating system instances on the processor concurrently.
* Cache enhancements: Montecito added a split L2 cache, which included a dedicated 1&nbsp;MB L2 cache for instructions. The original 256&nbsp;KB L2 cache was converted to a dedicated data cache. Montecito also included up to 12&nbsp;MB of on-die L3 cache.

== See also ==
* [[List of Intel Itanium microprocessors]]

== References ==
{{refs}}

== External links ==

* {{Webarchive|url=https://web.archive.org/web/20150121010330/https://www.intel.com/content/www/us/en/processors/itanium/itanium-processor-9000-sequence.html |title=Intel Itanium Processors}} <!-- – home page -->
* <!-- not longer selling, link "dead", or now only for x86, e.g. HPE Superdome Flex 280 Server -->[https://www.hpe.com/us/en/product-catalog/servers/integrity-servers.hits-12.html Hewlett Packard Enterprise Integrity Servers Home Page] {{Webarchive|url=https://web.archive.org/web/20170515102801/https://www.hpe.com/us/en/product-catalog/servers/integrity-servers.hits-12.html |date=2017-05-15 }}
* [https://www.intel.com/design/itanium/arch_spec.htm Intel Itanium Specifications]
* {{Webarchive|url=https://web.archive.org/web/20070223234225/http://www.gelato.unsw.edu.au/IA64wiki/ItaniumInternals |date=2007-02-23 |title=Some undocumented Itanium 2 microarchitectural information}}
* [https://web.archive.org/web/20110706223150/http://sverre.web.cern.ch/sverre/IA64_1.pdf IA-64 tutorial, including code examples]
* <!-- Intriguingly link now goes to login.microsoftonline.com page: --> [https://www.hp.com/go/integrity Itanium Docs at HP]

{{Intel processors}}
{{Authority control}}

[[Category:Computer-related introductions in 2001]]
[[Category:Instruction set architectures]]
[[Category:Intel microprocessors]]
[[Category:Very long instruction word computing]]
[[Category:64-bit computers]]