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{{Short description|Type of computer memory}}
{{Distinguish|text=[[Synchronous dynamic random-access memory]] (SDRAM)}}

[[File:Hyundai RAM HY6116AP-10.jpg|thumb|alt=|A static RAM chip from a [[Nintendo Entertainment System]] clone (2K × 8 bits)]]
{{Memory types}}

'''Static random-access memory''' ('''static RAM''' or '''SRAM''') is a type of [[random-access memory]] (RAM) that uses latching circuitry ([[Flip-flop (electronics)|flip-flop]]) to store each bit. SRAM is [[volatile memory]]; data is lost when power is removed.

The ''static'' qualifier differentiates SRAM from [[Dynamic random-access memory|''dynamic'' random-access memory]] (DRAM):
* SRAM will hold its data permanently in the presence of power, while data in DRAM decays in seconds and thus must be periodically [[memory refresh|refreshed]].
* SRAM is faster than DRAM but it is more expensive in terms of silicon area and cost.
* Typically, SRAM is used for the [[CPU cache|cache]] and internal [[CPU register|registers]] of a [[CPU]] while DRAM is used for a computer's [[main memory]].

==History==
Semiconductor bipolar SRAM was invented in 1963 by Robert Norman at [[Fairchild Semiconductor]].<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=[[Computer History Museum]] |access-date=19 June 2019 |archive-date=3 October 2019 |archive-url=https://web.archive.org/web/20191003072028/https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |url-status=live }}</ref> [[Metal–oxide–semiconductor]] SRAM (MOS-SRAM) was invented in 1964 by John Schmidt at [[Fairchild Semiconductor]]. The first device was a 64-bit MOS p-channel SRAM.<ref>{{cite web|title=1970: MOS dynamic RAM competes with magnetic core memory on price|url=https://www.computerhistory.org/siliconengine/mos-dynamic-ram-competes-with-magnetic-core-memory-on-price/|website=[[Computer History Museum]]|access-date=2020-10-08|archive-date=2021-10-26|archive-url=https://web.archive.org/web/20211026142915/https://www.computerhistory.org/siliconengine/mos-dynamic-ram-competes-with-magnetic-core-memory-on-price/|url-status=live}}</ref><ref>{{cite web |title=Memory lectures|url=https://faculty.kfupm.edu.sa/COE/mudawar/coe501/lectures/05-MainMemory.pdf}}</ref>

SRAM was the main driver behind any new [[CMOS]]-based technology fabrication process since the 1960s, when CMOS was invented.<ref name=":0">{{Cite web|last=Walker|first=Andrew|date=December 17, 2018|title=The Trouble with SRAM|url=https://www.eetimes.com/the-trouble-with-sram/|work=[[EE Times]]}}</ref>{{explain|reason=Was it the main driver or is it still the main driver? If it was the main driver, then we shouldn’t use the word ”since”, but instead ”between” and add an end time.|date=April 2026}}

In 1964, Arnold Farber and Eugene Schlig, working for IBM, created a hard-wired memory cell, using a [[transistor]] gate and [[tunnel diode]] [[Flip-flop (electronics)|latch]]. They replaced the latch with two transistors and two [[resistor]]s, a configuration that became known as the Farber-Schlig cell. That year they submitted an invention disclosure, but it was initially rejected.<ref>{{cite patent |country=US |number=3354440A |invent1=Arnold S. Farber |invent2=Eugene S. Schlig |assign1=IBM |title=Nondestructive memory array |gdate=1967-11-21}}{{dead link|date=January 2024}}</ref><ref>{{cite book | author1= Emerson W. Pugh | author2= Lyle R. Johnson | author3= John H. Palmer | title=IBM's 360 and Early 370 Systems | year=1991 | page=462 |publisher=MIT Press | isbn=9780262161237 | url=https://books.google.com/books?id=MFGj_PT_clIC}}</ref> In 1965, Benjamin Agusta and his team at IBM created a 16-bit silicon memory chip based on the Farber-Schlig cell, with 84 transistors, 64 resistors, and 4 diodes.

In April 1969, Intel Inc. introduced its first product, Intel 3101, a SRAM memory chip intended to replace bulky [[magnetic-core memory]] modules; Its capacity was 64 bits{{efn|In the first versions, only 63 bits were usable due to a bug.}}<ref>{{Cite journal |last1=Volk |first1=Andrew M. |last2=Stoll |first2=Peter A. |last3=Metrovich |first3=Paul |date=First Quarter 2001 |title=Recollections of Early Chip Development at Intel |url=https://www.intel.com/content/dam/www/public/us/en/documents/research/2001-vol05-iss-1-intel-technology-journal.pdf#page=11 |journal=Intel Technology Journal |volume=5 |issue=1 |pages=11 |via=Intel |archive-date=2022-01-12 |access-date=2024-01-23 |archive-url=https://web.archive.org/web/20220112103654/https://www.intel.com/content/dam/www/public/us/en/documents/research/2001-vol05-iss-1-intel-technology-journal.pdf#page=11 |url-status=live }}</ref> and was based on [[bipolar junction transistor]]s.<ref name=":2">{{Cite web |date=2018-05-14 |title=Intel at 50: Intel's First Product – the 3101 |url=https://newsroom.intel.com/news/intel-at-50-intels-first-product-3101/ |url-status=dead |archive-url=https://web.archive.org/web/20230201231900/https://newsroom.intel.com/news/intel-at-50-intels-first-product-3101/ |archive-date=2023-02-01 |access-date=2023-02-01 |website=Intel Newsroom |language=en-US}}</ref> It was designed by using [[rubylith]].<ref>{{Citation |title=Intel 64 bit static RAM rubylith : 6 |date=c. 1970 |url=https://www.computerhistory.org/collections/catalog/102718783 |access-date=2023-01-28 |archive-date=2023-01-28 |archive-url=https://web.archive.org/web/20230128201035/https://www.computerhistory.org/collections/catalog/102718783 |url-status=live }}</ref>

==Characteristics==
Though it can be characterized as [[volatile memory]], SRAM exhibits [[data remanence]].<ref name="skorobogatov">{{cite journal|title=Low temperature data remanence in static RAM|author=Sergei Skorobogatov|website=University of Cambridge, Computer Laboratory|date=June 2002|doi=10.48456/tr-536|url=http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-536.html|access-date=2008-02-27|archive-date=2019-01-18|archive-url=https://web.archive.org/web/20190118223747/https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-536.html|url-status=live}}</ref>

SRAM offers a simple data access model and does not require a refresh circuit. Performance and reliability are good and power consumption is low when idle. Since SRAM requires more transistors per bit to implement, it is less dense and more expensive than DRAM and also has a higher [[power consumption]] during read or write access. The power consumption of SRAM varies widely depending on how frequently it is accessed.<ref name="Null">{{cite book |last1=Null |first1=Linda |last2=Lobur |first2=Julia |url=https://books.google.com/books?id=QGPHAl9GE-IC |title=The Essentials of Computer Organization and Architecture |publisher=Jones and Bartlett Publishers |year=2006 |page=282 |isbn=978-0763737696 |accessdate=2021-09-14 }}</ref>

==Applications==
{{Multiple image
| direction = vertical
| width = 250
| header = RAM cells on the [[Die (integrated circuit)|die]] of a STM32F103VGT6 [[microcontroller]] manufactured by [[STMicroelectronics]] using a 180-[[nanometre]] process
| image1 = STM32-SEM-HD.jpg
| caption1 = Imaged by [[scanning electron microscope]]; cell [[topology]] is clearly visible
| image2 = STM32F103VGT6-SRAM.jpg
| caption2 = Imaged by [[optical microscope]]
}}

==={{anchor|EMBEDDED}}Embedded use===
Many categories of industrial and scientific subsystems, automotive electronics, and similar [[embedded system]]s, contain SRAM which, in this context, may be referred to as ''embedded SRAM'' (ESRAM).<ref>{{cite web |url=https://wccftech.com/microsoft-xbox-esram-huge-win-explains-reaching-1080p60-fps/ |title=Microsoft Says Xbox One's ESRAM is a "Huge Win" – Explains How it Allows Reaching 1080p/60 FPS |author=Fahad Arif |date=Apr 5, 2014 |access-date=2020-03-24 |archive-date=2020-03-24 |archive-url=https://web.archive.org/web/20200324175648/https://wccftech.com/microsoft-xbox-esram-huge-win-explains-reaching-1080p60-fps/ |url-status=live }}</ref> Some amount is also embedded in practically all modern appliances, toys, etc. that implement an electronic user interface.

SRAM in its [[dual-ported RAM|dual-ported]] form is sometimes used for real-time [[digital signal processing]] circuits.<ref>{{citation |title=Shared Memory Interface with the TMS320C54x DSP |url=https://www.ti.com/lit/an/spra441/spra441.pdf |access-date=2019-05-04 |archive-date=2019-05-04 |archive-url=https://web.archive.org/web/20190504142741/https://www.ti.com/lit/an/spra441/spra441.pdf |url-status=live }}</ref>

===In computers===
SRAM is used in personal computers, workstations and peripheral equipment: CPU [[register file]]s, internal [[CPU cache]]s and [[GPU cache]]s, [[hard disk]] buffers, etc. [[LCD screen]]s also may employ SRAM to hold the image displayed. SRAM was used for the main memory of many early personal computers such as the [[ZX80]], [[TRS-80 Model 100]], and [[VIC-20]].

Some early [[memory card]]s in the late 1980s to early 1990s used SRAM as a storage medium, which required a lithium battery to retain the contents of the SRAM.<ref name="auto1">{{Cite magazine |first=Nick |last=Stam |url=https://books.google.com/books?id=x2Fa5SDi0G8C&dq=memory+cards+SRAM+battery&pg=PA270 |title=PCMCIA's System Architecture |magazine=PC Mag |date=December 21, 1993 |publisher=Ziff Davis, Inc. |via=Google Books}}</ref><ref>{{Cite magazine|url=https://books.google.com/books?id=-Xr7Ic-ivyMC&dq=atari+portfolio+memory+card&pg=PT318 |first=Jonathan |last=Matzkin |title=$399 Atari Portfolio Takes on Hand-held Poqet PC |magazine=PC Mag |date=December 26, 1989|publisher=Ziff Davis, Inc. |via=Google Books}}</ref>

=== Integrated on chip ===
SRAM may be integrated on chip for:
* the RAM in [[microcontrollers]] (usually from around 32 bytes to a [[megabyte]]),
* the on-chip [[CPU cache|caches]] in most modern processors, like CPUs and GPUs, from a few [[kilobyte]]s and up to more than a hundred megabytes,
* the registers and parts of the state-machines used in CPUs, GPUs, [[chipset]]s and peripherals (see [[register file]]),
* [[scratchpad memory]],
* [[application-specific integrated circuit]]s (ASICs) (usually in the order of kilobytes),
* and in [[field-programmable gate array]]s (FPGAs) and [[complex programmable logic device]]s (CPLDs).

===Hobbyists===
Hobbyists, specifically home-built processor enthusiasts, often prefer SRAM due to the ease of interfacing. It is much easier to work with than DRAM as there are no refresh cycles<ref>{{Cite web|url=https://3.14.by/en/read/homemade-cpus|title=Homemade CPU – from scratch : Svarichevsky Mikhail|website=3.14.by|access-date=2024-01-27|archive-date=2024-01-27|archive-url=https://web.archive.org/web/20240127001443/https://3.14.by/en/read/homemade-cpus|url-status=live}}</ref> and the address and data buses are often directly accessible.{{Citation needed|date=May 2024}} In addition to buses and power connections, SRAM usually requires only three controls: Chip Enable (CE), Write Enable (WE) and Output Enable (OE). In synchronous SRAM, Clock (CLK) is also included.<ref>{{cite web |url=https://www.eeherald.com/section/design-guide/esmod15.html |title=Embedded Systems Course- module 15: SRAM memory interface to microcontroller in embedded systems |access-date=2024-04-12 |archive-date=2024-04-16 |archive-url=https://web.archive.org/web/20240416070225/https://www.eeherald.com/section/design-guide/esmod15.html |url-status=live }}</ref>

==Types of SRAM==

===Non-volatile SRAM===
[[Non-volatile SRAM]] (nvSRAM) has standard SRAM functionality, but retains data when power is lost. nvSRAMs are used in networking, aerospace, and medical, among other applications,<ref>{{cite book|title=Computer organization|url=https://archive.org/details/isbn_9780071143097|url-access=registration|publisher=McGraw-Hill|location=[S.l.]|isbn=978-0-07-114323-3|edition=4th|date=1996-07-01}}</ref> where the preservation of data is critical and where batteries are impractical.

==={{anchor|Pseudo SRAM}}Pseudostatic RAM===
[[Pseudostatic RAM]] (PSRAM) is DRAM combined with a self-refresh circuit.<ref>{{cite web |url=https://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/MT45V256KW16PEGA.pdf |title=3.0V Core Async/Page PSRAM Memory |publisher=Micron |ref=MT45V256 |access-date=2019-05-04 |archive-date=2018-08-24 |archive-url=https://web.archive.org/web/20180824135123/https://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/MT45V256KW16PEGA.pdf |url-status=live }}</ref> It appears externally as slower SRAM, albeit with a density and cost advantage over true SRAM, and without the access complexity of DRAM.

===By transistor type===
* [[Bipolar junction transistor]] (used in [[transistor-transistor logic|TTL]] and [[emitter coupled logic|ECL]]){{snd}}very fast but with high power consumption
* [[MOSFET]] (used in [[CMOS]]){{snd}}low power

=== By numeral system ===
* Binary
* [[Ternary numeral system|Ternary]]

===By function===
* [[Asynchronous circuit|Asynchronous]]{{snd}}independent of clock frequency, data in and data out are controlled by address transition. Examples include the ubiquitous 28-pin {{times|8K|8}} and {{times|32K|8}} chips (often but not always named something along the lines of [[6264]] and 62C256, respectively), as well as similar products up to 16 Mbit per chip.
* [[Synchronous]]{{snd}}all timings are initiated by the clock edges. Address, data in and other control signals are associated with the clock signals.

In the 1990s, asynchronous SRAM was employed for fast access time. Asynchronous SRAM was used as [[main memory]] for small cache-less embedded processors used in everything from [[industrial electronics]] and [[measurement system]]s to [[hard disk]]s and networking equipment. Synchronous SRAM (e.g., DDR SRAM) is preferred similarly to how synchronous DRAM{{snd}}[[DDR SDRAM]] memory is now preferred over [[asynchronous DRAM]]. The [[pipeline architecture]] employed by Synchronous memory allows higher throughput. Furthermore, as DRAM is much cheaper than SRAM, SRAM is often replaced by DRAM, especially in cases where a large memory capacity is required. SRAM memory is, however, much faster for random, as opposed to block or burst access. Therefore, SRAM memory is mainly used for [[CPU cache]], small on-chip memory, [[FIFO (electronic)|FIFO]]s or other small buffers.

===By feature===
* Zero bus turnaround (ZBT){{snd}}the turnaround is the number of clock cycles it takes to change access to SRAM from ''write'' to ''read'' and vice versa. The turnaround for ZBT SRAMs or the latency between read and write cycles is zero.
* syncBurst (syncBurst SRAM or synchronous-burst SRAM){{snd}}features synchronous burst write access to SRAM to increase write throughput to SRAM.
* DDR SRAM{{snd}}synchronous, single read/write port, double data rate I/O.
* [[Quad Data Rate SRAM]]{{snd}}synchronous, separate read and write ports, quadruple data rate I/O.

===By stacks===
* Single-stack SRAM
* 2.5D SRAM{{snd}}{{as of|2025|lc=on}}, 3D SRAM technology is still expensive, so SRAM with [[2.5D integrated circuit]] technology may be used.
* 3D SRAM{{snd}}used on various performance-oriented models of [[AMD]] processors.

==Design==
[[File:SRAM Cell (6 Transistors).svg|thumb|A six-transistor (6T) CMOS SRAM cell. WL: word line. BL: bit line.]]

A typical SRAM cell is made up of six [[MOSFET]]s, and is often called a '''{{abbr|6T|6 transistor}} SRAM cell'''. Each [[bit]] in the cell is stored on four [[transistor]]s (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two stable states, which are used to denote 0 and 1. Two additional ''access'' transistors serve to control the access to a storage cell during read and write operations. 6T SRAM is the most common kind of SRAM.<ref name="auto">{{Cite book|chapter=A Review of Low-Power Static Random Access Memory (SRAM) Designs |doi=10.1109/DevIC57758.2023.10134887 |s2cid=258984439 |title=2023 IEEE Devices for Integrated Circuit (DevIC) |date=2023 |last1=Rathi |first1=Neetu |last2=Kumar |first2=Anil |last3=Gupta |first3=Neeraj |last4=Singh |first4=Sanjay Kumar |pages=455–459 |isbn=979-8-3503-4726-5 }}</ref> In addition to 6T SRAM, other kinds of SRAM use 4, 5, 7,<ref>{{Cite book|url=https://books.google.com/books?id=rMsqBgAAQBAJ&dq=5+transistor+sram&pg=SA1-PA35|title=The VLSI Handbook|first=Wai-Kai|last=Chen|date=October 3, 2018|publisher=CRC Press|isbn=978-1-4200-0596-7 |via=Google Books}}</ref> 8, 9,<ref name="auto"/> 10<ref>{{Cite journal |doi = 10.1109/JSSC.2007.897148|bibcode = 2007IJSSC..42.2303K|title = A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM|last1 = Kulkarni|first1 = Jaydeep P.|last2 = Kim|first2 = Keejong|last3 = Roy|first3 = Kaushik|journal = IEEE Journal of Solid-State Circuits|volume = 42|issue = 10|pages = 2303|year = 2007|s2cid = 699469}}</ref> (4T, 5T, 7T 8T, 9T, 10T SRAM), or more transistors per bit.<ref>{{cite web | title=0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM | date=March 2011 | pages=1–4 | doi=10.1109/ISQED.2011.5770728 | s2cid=6397769 }}</ref><ref>United States Patent 6975532: [https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051213&DB=EPODOC&locale=en_EP&CC=US&NR=6975532B1&KC=B1&ND=4 Quasi-static random access memory] {{Webarchive|url=https://web.archive.org/web/20230129214840/https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051213&DB=EPODOC&locale=en_EP&CC=US&NR=6975532B1&KC=B1&ND=4 |date=2023-01-29 }}</ref><ref>{{Cite web | url=http://ietele.oxfordjournals.org/cgi/content/abstract/E90-C/10/1949 | title=Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes -- MORITA et al. E90-C (10): 1949 -- IEICE Transactions on Electronics| url-status=dead | archive-url=https://web.archive.org/web/20081205085037/http://ietele.oxfordjournals.org/cgi/content/abstract/E90-C/10/1949| archive-date=2008-12-05}}</ref>

Additional transistors are sometimes used to implement more than one (read and/or write) port, which may be useful in certain types of [[video memory]] and [[register file]]s implemented with multi-ported SRAM circuitry.

Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory.

[[File:SRAM Cell (4 Transistors).svg|thumb|A four-transistor (4T) SRAM provides advantages in density at the cost of manufacturing complexity. The resistors must have small dimensions and large values.]]

Four-transistor SRAM is common in stand-alone SRAM devices (as opposed to SRAM used for CPU caches), implemented in special processes with an extra layer of [[polysilicon]], allowing for very high-resistance pull-up resistors.<ref>{{cite book |last1=Preston |first1=Ronald P. |chapter=14: Register Files and Caches |chapter-url=http://courses.engr.illinois.edu/ece512/Papers/Preston_2001_CBF.pdf |year=2001 |title=The Design of High Performance Microprocessor Circuits |publisher=IEEE Press |page=290 |access-date=2013-02-01 |archive-date=2013-05-09 |archive-url=https://web.archive.org/web/20130509010902/http://courses.engr.illinois.edu/ece512/Papers/Preston_2001_CBF.pdf |url-status=dead }}</ref> The principal drawback of using 4T SRAM is increased [[CMOS#Power: switching and leakage|static power]] due to the constant current flow through one of the pull-down transistors (M1 or M2).

Memory cells that use fewer than four transistors are possible; however, such 3T<ref>United States Patent 6975531: [http://www.freepatentsonline.com/6975531.html 6F2 3-transistor DRAM gain cell] {{Webarchive|url=https://web.archive.org/web/20200807141320/http://www.freepatentsonline.com/6975531.html |date=2020-08-07 }}</ref><ref>{{Cite web |url=https://tezzaron.com/3t-iram/ |title=3T-iRAM(r) Technology |access-date=2018-08-13 |archive-date=2018-08-13 |archive-url=https://web.archive.org/web/20180813210554/https://tezzaron.com/3t-iram/ |url-status=live }}</ref> or 1T cells are DRAM, not SRAM (even the so-called [[1T-SRAM]]).

Access to the cell is enabled by the word line (WL in figure) which controls the two ''access'' transistors M5 and M6 in 6T SRAM figure (or M3 and M4 in 4T SRAM figure) which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations.

During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs{{snd}}in a DRAM, the bit line is connected to storage capacitors, and [[charge sharing]] causes the bit line to swing upwards or downwards. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve [[noise margin]]s and speed. The symmetric structure of SRAMs also allows for [[differential signaling]], which makes small voltage swings more easily detectable.

Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e., higher bits followed by lower bits, over the same package pins in order to keep their size and cost down. The size of an SRAM with {{mvar|m}} address lines and {{mvar|n}} data lines is {{math|2''m''}} words, or {{math|2''m'' × ''n''}} bits. The most common word size is 8 bits, meaning that a single byte can be read or written to each of {{math|2''m''}} different words within the SRAM chip. Several common SRAM chips have 11 address lines (thus a capacity of 211 = 2,048 = 2 [[kibi (binary prefix)|k]] words) and an 8-bit word, so they are referred to as ''2k × 8 SRAM''.

The dimensions of an SRAM cell on an IC are determined by the [[minimum feature size]] of the process used to make the IC.
{{clear}}

==SRAM operation==
{{how-to|section|date=January 2023}}
An SRAM cell has three states:

* '''Standby:''' The circuit is idle.
* '''Reading:''' The data has been requested.
* '''Writing:''' Updating the contents.

SRAM operating in read and write modes should have ''readability'' and ''write stability'', respectively. The three different states work as follows:

===Standby===
If the word line is not asserted, the ''access'' transistors M5 and M6 disconnect the cell from the bit lines. The two cross-coupled inverters formed by M1{{snd}}M4 will continue to reinforce each other as long as power is available.

===Reading===
In theory, reading only requires activating a single access transistor and bit line, e.g. M6 on BL. However, in larger memories, bit lines are relatively long with many connections and thus have large capacitance. To speed up reading, a more complex process is used in practice. The read cycle is started by precharging both bit lines BL and BL, to high (logic 1) voltage.{{efn|As the NMOS transistor is more powerful, the pull-down is easier. Therefore, bit lines are traditionally precharged to a high voltage. Many researchers are also trying to precharge at a slightly lower voltage to reduce power consumption.<ref>{{Cite journal|url=https://www.tandfonline.com/doi/full/10.1080/1023697X.2014.970761|title=SRAM precharge system for reducing write power|first1=Hussain Mohammed Dipu|last1=Kabir|first2=Mansun|last2=Chan|date=January 2, 2015|journal=HKIE Transactions|volume=22|issue=1|pages=1–8|via=CrossRef|doi=10.1080/1023697X.2014.970761|s2cid=108574841|url-access=subscription|archive-date=January 27, 2024|access-date=January 27, 2024|archive-url=https://web.archive.org/web/20240127001442/https://www.tandfonline.com/doi/full/10.1080/1023697X.2014.970761|url-status=live}}</ref><ref>{{Cite web|url=https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.119.3735|title=CiteSeerX|website=CiteSeerX|citeseerx=10.1.1.119.3735 }}</ref>}} Then asserting the word line WL enables both the access transistors M5 and M6, which causes an initial slight drop on one bit line voltage creating a voltage difference between BL and BL. A [[differential amplifier|differential sense amplifier]] will sense which line has the higher voltage and thus determine whether there was 1 or 0 stored. Because motion of the bit lines is slowed by capacitance, the higher the sensitivity of the sense amplifier, the faster the read operation.

===Writing===
The write cycle begins by applying the value to be written to the bit lines. To write a 0, a 0 is applied to the bit lines, such as setting BL to 1 and BL to 0. This is similar to applying a reset pulse to an [[Latch (electronic)|SR-latch]], which causes the flip flop to change state. A '''1''' is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. This works because the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself so they can easily override the previous state of the cross-coupled inverters. In practice, access NMOS transistors M5 and M6 have to be stronger than either bottom NMOS (M1, M3) or top PMOS (M2, M4) transistors. This is easily obtained as PMOS transistors are much weaker than NMOS when same sized. Consequently, when one transistor pair (e.g. M3 and M4) is only slightly overridden by the write process, the opposite transistors pair (M1 and M2) gate voltage is also changed. This means that the M1 and M2 transistors can be easier overridden, and so on. Thus, cross-coupled inverters magnify the writing process.

===Bus behavior===
[[RAM]] with an access time of 70 ns will output valid data within 70 ns from the time that the address lines are valid. Some SRAM cells have a ''page mode'', where words of a page (256, 512, or 1024 words) can be read sequentially with a significantly shorter access time (typically approximately 30 ns). The page is selected by setting the upper address lines and then words are sequentially read by stepping through the lower address lines.

== Production challenges ==
Over 30 years (from 1987 to 2017), with a steadily decreasing [[Semiconductor device fabrication|transistor size]] (node size), the footprint-shrinking of the SRAM cell topology itself slowed down, making it harder to pack the cells more densely.<ref name=":0" /> One of the reasons is that scaling down transistor size leads to SRAM reliability issues. Careful cells designs are necessary to achieve SRAM cells that do not suffer from stability problems especially when they are being read.<ref>{{Cite journal |last1=Torrens |first1=Gabriel |last2=Alorda |first2=Bartomeu |last3=Carmona |first3=Cristian |last4=Malagon-Perianez |first4=Daniel |last5=Segura |first5=Jaume |last6=Bota |first6=Sebastia |date=2019 |title=A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors |journal=IEEE Transactions on Emerging Topics in Computing |volume=7 |issue=3 |pages=447–455 |arxiv=2411.18114 |doi=10.1109/TETC.2017.2721932 |bibcode=2019ITETC...7..447T |issn=2168-6750}}</ref> With the introduction of the [[FinFET]] transistor implementation of SRAM cells, they started to suffer from increasing inefficiencies in cell sizes.

Besides issues with size a significant challenge of modern SRAM cells is a static current leakage. The current, that flows from positive supply (Vdd), through the cell, and to the ground, increases exponentially when the cell's temperature rises. The cell power drain occurs in both active and idle states, thus wasting useful energy without any useful work done. Even though in the last 20 years the issue was partially addressed by the Data Retention Voltage technique (DRV) with reduction rates ranging from 5 to 10, the decrease in node size caused reduction rates to fall to about 2.<ref name=":0" />

With these two issues it became more challenging to develop energy-efficient and dense SRAM memories, prompting semiconductor industry to look for alternatives such as [[STT-MRAM]] and [[F-RAM]].<ref name=":0" /><ref>{{Cite web|last=Walker|first=Andrew|date=February 6, 2019|title=The Race is On|url=https://www.eetimes.com/the-race-is-on/|publisher=[[EE Times]]|access-date=November 30, 2021|archive-date=November 30, 2021|archive-url=https://web.archive.org/web/20211130191636/https://www.eetimes.com/the-race-is-on/|url-status=live}}</ref>

=== Research ===
In 2019 a French institute reported on a research of an [[IoT]]-purposed [[Semiconductor device fabrication|28nm]] fabricated [[Integrated circuit|IC]].<ref name=":1">{{Cite web|last=Reda|first=Boumchedda|date=May 20, 2019|title=Ultra-low voltage and energy efficient SRAM design with new technologies for IoT applications|url=https://tel.archives-ouvertes.fr/tel-03359929/document|publisher=[[Grenoble Alpes University]]|access-date=November 30, 2021|archive-date=November 30, 2021|archive-url=https://web.archive.org/web/20211130191639/https://tel.archives-ouvertes.fr/tel-03359929/document|url-status=live}}</ref> It was based on [[Silicon on insulator|fully depleted silicon on insulator]]-transistors (FD-SOI), had two-ported SRAM memory rail for synchronous/asynchronous accesses, and selective [[virtual ground]] (SVGND). The study claimed reaching an ultra-low SVGND current in a ''sleep'' and read modes by finely tuning its voltage.<ref name=":1" />

==See also==
{{Commons category multi|SRAM|CMOS_RAM}}
* [[Flash memory]]
* [[Miniature Card]], a discontinued SRAM memory card standard
* [[In-memory processing]]

==Notes==
{{Notelist}}

==References==
{{Reflist}}

{{Primary storage technologies}}

{{Authority control}}

{{DEFAULTSORT:Static Random Access Memory}}
[[Category:Computer memory]]
[[Category:Random-access memory]]

Static random-access memory - Revision history

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