Complex instruction set computer: Difference between revisions

A '''complex instruction set computer''' ('''CISC''' {{IPAc-en|ˈ|s|ɪ|s|k}}) is a [[computer architecture]] in which single [[instruction set architecture|instruction]]s can execute several low-level operations (such as a load from [[Memory (computers)|memory]], an [[arithmetic]] [[operator (programming)|operation]], and a memory store) or are capable of multi-step operations or [[addressing mode]]s within single instructions.{{Citation needed|date=November 2023}} The term was retroactively coined in contrast to [[reduced instruction set computer]] (RISC)<ref>{{cite journal|title=The case for the reduced instruction set computer|journal=ACM SIGARCH Computer Architecture News|last1= Patterson|first1=D. A.|author-link1=David A. Patterson (scientist)|last2=Ditzel|first2= D. R.|date=October 1980|volume=8|issue=6|pages=25–33|publisher=[[Association for Computing Machinery|ACM]]|doi=10.1145/641914.641917|s2cid=12034303}}</ref> and has therefore become something of an [[umbrella term]] for everything that is not RISC,{{Citation needed|date=November 2023}} where the typical differentiating characteristic{{dubious|date=April 2023|reason=It would be nice to have one characteristic to differentiate RISC and CISC but most sources give a handful of factors.}} is that most RISC designs use uniform instruction length for almost all instructions, and employ strictly separate load and store instructions.

Examples of CISC architectures include complex [[mainframe computer]]s to simplistic microcontrollers where memory load and store operations are not separated from arithmetic instructions.{{Citation needed|date=November 2023}} Specific instruction set architectures that have been retroactively labeled CISC are [[System/360]] through [[z/Architecture]], the [[PDP-11]] and [[VAX]] architectures, and many others. Well known microprocessors and microcontrollers that have also been labeled CISC in many academic publications{{citation needed|date=April 2023|reason=which publications?}} include the [[Motorola 6800]], [[6809]] and [[Motorola 68000 series|68000]] families; the Intel [[8080]], [[iAPX 432]], [[x86]] and [[8051]] families; the Zilog [[Z80]], [[Zilog Z8|Z8]] and [[Z8000]] families; the [[National Semiconductor]] [[NS32000|NS320xx]] family; the MOS Technology [[6502]] family; and others.

Before the RISC philosophy became prominent, many computer architects tried to bridge the so-called [[semantic gap]], i.e., to design instruction sets that directly support high-level programming constructs such as procedure calls, loop control, and complex [[addressing mode]]s, allowing data structure and array accesses to be combined into single instructions. Instructions are also typically highly encoded in order to further enhance the code density. The compact nature of such instruction sets results in smaller [[Computer program|program]] sizes and fewer main memory accesses (which were often slow), which at the time (early 1960s and onwards) resulted in a tremendous saving on the cost of computer memory and disc storage, as well as faster execution. It also meant good [[programming productivity]] even in [[assembly language]], as [[high level language]]s such as [[Fortran]] or [[ALGOL|Algol]] were not always available or appropriate. Indeed, microprocessors in this category are sometimes still programmed in assembly language for certain types of critical applications.{{Citation needed|date=October 2011}}

In the 1970s, analysis of high-level languages indicated compilers produced some complex corresponding machine language. It was determined that new instructions could improve performance. Some instructions were added that were never intended to be used in assembly language but fit well with compiled high-level languages. Compilers were updated to take advantage of these instructions. The benefits of semantically rich instructions with compact encodings can be seen in modern processors as well, particularly in the high-performance segment where caches are a central component (as opposed to most [[embedded system]]s). This is because these fast, but complex and expensive, memories are inherently limited in size, making compact code beneficial. Of course, the fundamental reason they are needed is that main memories (i.e., [[dynamic RAM]] today) remain slow compared to a (high-performance) CPU core.

By the mid-1980s the computer industry's consensus was that RISC was more efficient than CISC. [[Digital Equipment Corporation]] estimated that RISC had a [[price/performance ratio]] at least twice that of CISC. Two possible responses from CISC vendors were:<ref name="bellstreckerpdp11vaxalpha">{{Cite report |url=https://archive.computerhistory.org/resources/text/DEC/alpha/dec.alpha.bell_stecker.pdp-11_vax_and_alpha.1998.102630388.pdf |title=What Have We Learned from the PDP-11 - What We Have Learned from VAX and Alpha |last=Bell |first=Gordon |author-link=Gordon Bell |last2=Strecker |first2=W.D. |access-date=2025-06-26}}</ref>

Intel was successful in improving x86 to match RISC's performance.<ref name="forbes20031009">{{Cite magazine |date=2003-10-09 |title=Ex-Apple CEO Regrets Nixing Intel |url=https://www.forbes.com/2003/10/09/1009intelpinnacor.html |access-date=2025-06-28 |magazine=Forbes |language=en}}</ref> The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly (or tightly) pipelined x86 implementations, the 486 designs from Intel, [[AMD]], [[Cyrix]], and IBM, supported every instruction that their predecessors did, but achieved ''maximum efficiency'' only on a fairly simple x86 subset that was only a little more than a typical RISC instruction set (i.e., without typical RISC ''[[load–store architecture|load–store]]'' limits).{{Citation needed|date=November 2023}} The Intel [[P5 (microarchitecture)|P5]] [[Pentium]] generation was a superscalar version of these principles. However, modern x86 processors also (typically) decode and split instructions into dynamic sequences of internally buffered [[micro-operation]]s, which helps execute a larger subset of instructions in a pipelined (overlapping) fashion, and facilitates more advanced extraction of parallelism out of the code stream, for even higher performance.

Contrary to popular simplifications (present also in some academic texts,) not all CISCs are microcoded or have "complex" instructions.{{Citation needed|date=November 2023}} As CISC became a catch-all term meaning anything that's not a load–store (RISC) architecture, it's not the number of instructions, nor the complexity of the implementation or of the instructions, that define CISC, but that arithmetic instructions also perform memory accesses.<ref>{{Cite book |last1=Hennessy |first1=John |author-link1=John L. Hennessy |last2=Patterson |first2=David |author-link2=David Patterson (computer scientist) |title=Computer Architecture: A Quantitative Approach |url=http://acs.pub.ro/~cpop/SMPA/Computer%20Architecture,%20Sixth%20Edition_%20A%20Quantitative%20Approach%20(%20PDFDrive%20).pdf |url-status=live |archive-url=https://web.archive.org/web/20230614014543/http://acs.pub.ro/~cpop/SMPA/Computer%20Architecture,%20Sixth%20Edition_%20A%20Quantitative%20Approach%20%28%20PDFDrive%20%29.pdf |archive-date=June 14, 2023 |access-date=June 13, 2023}}</ref>{{Failed verification|date=June 2023|reason=The book doesn't mention CISC.}} Compared to a small 8-bit CISC processor, a RISC floating-point instruction is complex. CISC does not even need to have complex addressing modes; 32- or 64-bit RISC processors may well have more complex addressing modes than small 8-bit CISC processors.

A [[PDP-10]], a [[PDP-8]], an x86 processor, an [[Intel 4004]], a Motorola 68000-series processor, a [[IBM Z]] mainframe, a [[Burroughs B5000]], a [[VAX]], a [[Zilog Z80000]], and a [[MOS Technology 6502]] all vary widely in the number, sizes, and formats of instructions, the number, types, and sizes of registers, and the available data types. Some have hardware support for operations like scanning for a substring, arbitrary-precision BCD arithmetic, or [[transcendental function]]s, while others have only 8-bit addition and subtraction. But they are all in the CISC category{{Citation needed|reason=This is a controversial and ahistorical claim|date=March 2023}}. because they have "load-operate" instructions that load and/or store memory contents within the same instructions that perform the actual calculations. For instance, the PDP-8, having only 8 fixed-length instructions and no microcode at all, is a CISC because of ''how'' the instructions work, PowerPC, which has over 230 instructions (more than some VAXes), and complex internals like register renaming and a reorder buffer, is a RISC, while [[Minimal CISC]] has 8 instructions, but is clearly a CISC because it combines memory access and computation in the same instructions.