Data General Nova: Difference between revisions
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| os = [[Data General RDOS|RDOS]] | | os = [[Data General RDOS|RDOS]] | ||
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[[File:Data General NOVA System.jpg|thumb|A Nova system (beige and yellow, center bottom) and a cartridge hard disk system (opened, below Nova) in a mostly empty rack mount]] | [[File:Data General NOVA System.jpg|thumb|A Nova 3 system (beige and yellow, center bottom) and a cartridge hard disk system (opened, below Nova) in a mostly empty rack mount]] | ||
[[File:Emi1010.jpg|thumb|288px|right|A Nova | [[File:Emi1010.jpg|thumb|288px|right|A Nova 820, mid-right, processed the images generated by the EMI-Scanner, the world's first commercially available [[CT scan]]ner.]] | ||
The '''Nova''' is a series of [[16-bit computing|16-bit]] [[minicomputer]]s released by the American company [[Data General]]. The Nova family was very popular in the 1970s and ultimately sold tens of thousands of units. | The '''Nova''' is a series of [[16-bit computing|16-bit]] [[minicomputer]]s released by the American company [[Data General]]. The Nova family was very popular in the 1970s and ultimately sold tens of thousands of units. | ||
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===Edson de Castro and the PDP-X=== | ===Edson de Castro and the PDP-X=== | ||
[[Edson de Castro]] was the Product Manager of the pioneering [[Digital Equipment Corporation]] (DEC) [[PDP-8]], a 12-bit computer widely referred to as the first true minicomputer.<ref>{{cite book |url=https://books.google.com/books?id=NrMkBQAAQBAJ&pg=PA165 |title=The Computing Universe: A Journey through a Revolution |first1=Tony |last1=Hey |first2=Anthony |last2=Hey |first3=Gyuri |last3=Pápay |date=2014 |page=165 |publisher=Cambridge University Press |isbn=9780521766456}}</ref> He also led the design of the upgraded PDP-8/I, which used early [[integrated circuit]]s in place of individual transistors.{{sfn|Hendrie|2002|p=40}} | [[Edson de Castro]] was the [[Product manager|Product Manager]] of the pioneering [[Digital Equipment Corporation]] (DEC) [[PDP-8]], a 12-bit computer widely referred to as the first true minicomputer.<ref>{{cite book |url=https://books.google.com/books?id=NrMkBQAAQBAJ&pg=PA165 |title=The Computing Universe: A Journey through a Revolution |first1=Tony |last1=Hey |first2=Anthony |last2=Hey |first3=Gyuri |last3=Pápay |date=2014 |page=165 |publisher=Cambridge University Press |isbn=9780521766456}}</ref> He also led the design of the upgraded PDP-8/I, which used early [[integrated circuit]]s in place of individual transistors.{{sfn|Hendrie|2002|p=40}} | ||
During the PDP-8/I process, de Castro had been visiting [[printed circuit board|circuit board]] manufacturers who were making rapid advances in the complexity of the boards they could assemble. de Castro concluded that the 8/I could be produced using fully automated assembly on large boards, which would have been impossible only a year earlier. Others within DEC had become used to the smaller boards used in earlier machines and were concerned about tracking down problems when there were many components on a single board.{{efn|This was likely a reaction to the problems with the [[PDP-6]], which used large boards and had significant failure rates. The [[PDP-10]], essentially a re-engineered PDP-6, uses smaller "flip-chip" cards.}} For the 8/I, the decision was made to stay with small boards, using the new "[[Flip-Chip module|flip-chip]]" packaging for a modest improvement in density.{{sfn|Hendrie|2002|p=40}} | During the PDP-8/I process, de Castro had been visiting [[printed circuit board|circuit board]] manufacturers who were making rapid advances in the complexity of the boards they could assemble. de Castro concluded that the 8/I could be produced using fully automated assembly on large boards, which would have been impossible only a year earlier. Others within DEC had become used to the smaller boards used in earlier machines and were concerned about tracking down problems when there were many components on a single board.{{efn|This was likely a reaction to the problems with the [[PDP-6]], which used large boards and had significant failure rates. The [[PDP-10]], essentially a re-engineered PDP-6, uses smaller "flip-chip" cards.}} For the 8/I, the decision was made to stay with small boards, using the new "[[Flip-Chip module|flip-chip]]" packaging for a modest improvement in density.{{sfn|Hendrie|2002|p=40}} | ||
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===Design=== | ===Design=== | ||
Cancelation of the PDP-X prompted de Castro to consider leaving DEC to build a system on his own. He was not alone; in late 1967 a | Cancelation of the PDP-X prompted de Castro to consider leaving DEC to build a system on his own. He was not alone; in late 1967 a number of like-minded engineers formed a group to consider such a machine. The group included Pat Green, a divisional manager; Richard Sogge, another hardware engineer; and Henry Burkhardt III, a software engineer.<ref>{{cite web |url=http://www.cpushack.com/2014/11/21/when-a-minicomputer-becomes-a-micro-the-dgc-micronova-mn601-and-602/ |title=When a Minicomputer becomes a Micro: the DGC microNOVA mN601 and 602 |date=21 November 2014 |website=The CPU Shack Museum}}</ref> In contrast to the PDP-X, the new effort focused on a single machine that could be brought to market quickly, as de Castro felt the PDP-X concept was far too ambitious for a small [[startup company]].{{sfn|Hendrie|2002|p=43}} | ||
Discussing it with the others at DEC, the initial concept led to an 8-bit machine which would be less costly to implement.{{sfn|Hendrie|2002|p=43-44}} The group began talking with Herbert Richman, a salesman for [[Fairchild Semiconductor]] who knew the others through his contacts with DEC. At the time, Fairchild was battling with [[Texas Instruments]] and [[Signetics]] in the rapidly growing [[transistor-transistor logic|TTL]] market and were introducing new [[semiconductor device fabrication|fabs]] that allowed more complex designs. Fairchild's latest 9300 series allowed up to 96 gates per chip, and they had used this to implement a number of 4-bit chips like binary counters and [[shift register]]s.<ref name="Gianluca G.">{{cite web |url=https://apollo181.wixsite.com/apollo181/about |title=History of ALU 74181 in commercial minicomputers |author=Gianluca G. |date=2017}}</ref> | Discussing it with the others at DEC, the initial concept led to an 8-bit machine which would be less costly to implement.{{sfn|Hendrie|2002|p=43-44}} The group began talking with Herbert Richman, a salesman for [[Fairchild Semiconductor]] who knew the others through his contacts with DEC. At the time, Fairchild was battling with [[Texas Instruments]] and [[Signetics]] in the rapidly growing [[transistor-transistor logic|TTL]] market and were introducing new [[semiconductor device fabrication|fabs]] that allowed more complex designs. Fairchild's latest 9300 series allowed up to 96 gates per chip, and they had used this to implement a number of 4-bit chips like binary counters and [[shift register]]s.<ref name="Gianluca G.">{{cite web |url=https://apollo181.wixsite.com/apollo181/about |title=History of ALU 74181 in commercial minicomputers |author=Gianluca G. |date=2017 |access-date=2023-01-01 |archive-date=2018-10-07 |archive-url=https://web.archive.org/web/20181007001841/http://apollo181.wixsite.com/apollo181/about |url-status=dead }}</ref> | ||
Using these ICs reduced the total IC count needed to implement a complete [[arithmetic logic unit]] (ALU), the core mathematical component of a CPU, allowing the expansion from an 8-bit design to 16-bit. This did require the expansion of the CPU from a single {{convert|15|x|15|in|cm}} [[printed circuit board]] to two, but such a design would still be significantly cheaper to produce than the PDP-8/I while still being more powerful and ASCII-based. A third board held the [[input/output]] circuitry and a complete system typically included another board with 4 kB of [[random-access memory]]. A complete four-card system fit in a single rackmount chassis.{{sfn|Hendrie|2002|p=48}} | Using these ICs reduced the total IC count needed to implement a complete [[arithmetic logic unit]] (ALU), the core mathematical component of a CPU, allowing the expansion from an 8-bit design to 16-bit. This did require the expansion of the CPU from a single {{convert|15|x|15|in|cm}} [[printed circuit board]] to two, but such a design would still be significantly cheaper to produce than the PDP-8/I while still being more powerful and ASCII-based. A third board held the [[input/output]] circuitry and a complete system typically included another board with 4 kB of [[random-access memory]]. A complete four-card system fit in a single rackmount chassis.{{sfn|Hendrie|2002|p=48}} | ||
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The first sale was to a university in Texas, with the team hand-building an example which shipped out in February. However, this was in the midst of a strike in the airline industry and the machine never arrived. They sent a second example, which arrived promptly as the strike had ended by that point, and in May the original one was finally delivered as well.{{sfn|Hendrie|2002|p=50}} | The first sale was to a university in Texas, with the team hand-building an example which shipped out in February. However, this was in the midst of a strike in the airline industry and the machine never arrived. They sent a second example, which arrived promptly as the strike had ended by that point, and in May the original one was finally delivered as well.{{sfn|Hendrie|2002|p=50}} | ||
The system was successful from the start, with the 100th being sold after six months,<ref name=supernova/> and the 500th after 15 months.<ref name=thwart>{{cite web |url=https://www.computerhistory.org/revolution/minicomputers/11/338 |title=Thwarted at DEC, Thriving at Data General |website=Computer History Museum}}</ref> Sales accelerated as newer versions were introduced, and by 1975 the company had annual sales of {{US$|100 million}}.<ref name=cnnmoney>{{cite web |title=The Business That Time Forgot: Data General is gone. But does that make its founder a failure? |date=1 April 2003 |url=https://money.cnn.com/magazines/fsb/fsb_archive/2003/04/01/341000/ |website=money.cnn.com |access-date=27 July 2016}}</ref> | The system was successful from the start, with the 100th being sold after six months,<ref name=supernova/> and the 500th after 15 months.<ref name=thwart>{{cite web |url=https://www.computerhistory.org/revolution/minicomputers/11/338 |title=Thwarted at DEC, Thriving at Data General |website=Computer History Museum}}</ref> Sales accelerated as newer versions were introduced, and by 1975 the company had annual sales of {{US$|100 million}}.<ref name=cnnmoney>{{cite web |title=The Business That Time Forgot: Data General is gone. But does that make its founder a failure? |date=1 April 2003 |url=https://money.cnn.com/magazines/fsb/fsb_archive/2003/04/01/341000/ |archive-url=https://web.archive.org/web/20140726003316/http://money.cnn.com/magazines/fsb/fsb_archive/2003/04/01/341000 |url-status=dead |archive-date=July 26, 2014 |website=money.cnn.com |access-date=27 July 2016}}</ref> | ||
===SuperNOVA=== | ===SuperNOVA=== | ||
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===Later models=== | ===Later models=== | ||
By this time, the PDP-11 was finally shipping. It offered a much richer [[instruction set architecture]] than the deliberately simple one in the Nova. Continuing improvement in IC designs, and especially their [[price–performance ratio]], was eroding the value of the original simplified instructions. Seligman was put in charge of designing a new machine that would be compatible with the Nova while offering a much richer environment for those who wanted it. This concept shipped as the [[Data General Eclipse]] series, which offered the ability to add additional circuitry to tailor the instruction set for scientific or data processing workloads. The Eclipse was successful in competing with the PDP-11 at the higher end of the market.{{sfn|Hendrie|2002|p=58}} | By this time, the PDP-11 was finally shipping. It offered a much richer [[instruction set architecture]] than the deliberately simple one in the Nova. Continuing improvement in IC designs, and especially their [[price–performance ratio]], was eroding the value of the original simplified instructions. Seligman was put in charge of designing a new machine that would be compatible with the Nova while offering a much richer environment for those who wanted it. This concept shipped as the [[Data General Eclipse]] series, which offered the ability to add additional circuitry to tailor the instruction set for scientific or [[data processing]] workloads. The Eclipse was successful in competing with the PDP-11 at the higher end of the market.{{sfn|Hendrie|2002|p=58}} | ||
Around the same time, rumors of a new 32-bit machine from DEC began to surface. DG decided they had to have a similar product, and Gruner was put in charge of what became the Fountainhead Project. Given the scope of the project, they agreed that the entire effort should be handled off-site, and Gruner selected a location at [[Research Triangle Park]] in [[North Carolina]]. This design became very complex{{sfn|Hendrie|2002|p=60}} and was ultimately canceled years later. | Around the same time, rumors of a new 32-bit machine from DEC began to surface. DG decided they had to have a similar product, and Gruner was put in charge of what became the Fountainhead Project. Given the scope of the project, they agreed that the entire effort should be handled off-site, and Gruner selected a location at [[Research Triangle Park]] in [[North Carolina]]. This design became very complex{{sfn|Hendrie|2002|p=60}} and was ultimately canceled years later. | ||
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====840==== | ====840==== | ||
The 840, first offered in 1973, also included a new paged memory system allowing for addresses of up to 17-bits. An index offset the base address into the larger 128 kword memory. Actually installing this much memory required considerable space; the 840 shipped in a large 14-slot case. | The 840, first offered in 1973, also included a new paged memory system allowing for addresses of up to 17-bits. An index offset the [[base address]] into the larger 128 kword memory. Actually installing this much memory required considerable space; the 840 shipped in a large 14-slot case. | ||
====Nova 2==== | ====Nova 2==== | ||
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===Legacy=== | ===Legacy=== | ||
The Nova influenced the design of both the [[Xerox Alto]] (1973)<ref>{{cite web |url=http://www.bitsavers.org/pdf/xerox/alto/memos_1974/Alto_A_Personal_Computer_Dec74.pdf |archive-url=https://web.archive.org/web/20110606164257/http://www.bitsavers.org/pdf/xerox/alto/memos_1974/Alto_A_Personal_Computer_Dec74.pdf |archive-date=2011-06-06 |url-status=live |title=Alto: A Personal Computer System |author1=Charles P. Thacker |author2=Edward M. McCreight |page=13 |date=December 1974}}</ref> and [[Apple I]] (1976)<ref>{{cite book |title=Apple I Replica Creation: Back to the Garage |author=Tom Owad |page=xxi |isbn=1-931836-40-X |date=2005}}</ref> computers, and its architecture was the basis for the [[Computervision]] CGP (Computervision Graphics Processor) series. Its external design has been reported to be the direct inspiration for the front panel of the [[Altair 8800|MITS Altair]] (1975) microcomputer. | The Nova influenced the design of both the [[Xerox Alto]] (1973)<ref>{{cite web |url=http://www.bitsavers.org/pdf/xerox/alto/memos_1974/Alto_A_Personal_Computer_Dec74.pdf |archive-url=https://web.archive.org/web/20110606164257/http://www.bitsavers.org/pdf/xerox/alto/memos_1974/Alto_A_Personal_Computer_Dec74.pdf |archive-date=2011-06-06 |url-status=live |title=Alto: A Personal Computer System |author1=Charles P. Thacker |author2=Edward M. McCreight |page=13 |date=December 1974}}</ref> and [[Apple I]] (1976)<ref>{{cite book |title=Apple I Replica Creation: Back to the Garage |author=Tom Owad |page=xxi |isbn=1-931836-40-X |date=2005}}</ref> computers, and its architecture was the basis for the [[Computervision]] CGP (Computervision Graphics Processor) series. Its external design has been reported to be the direct inspiration for the front panel of the [[Altair 8800|MITS Altair]] (1975) [[microcomputer]]. | ||
Data General followed up on the success of the original Nova with a series of faster designs. The Eclipse family of systems was later introduced with an extended upwardly compatible instruction set, and the MV-series further extended the Eclipse into a 32-bit architecture to compete with the DEC [[VAX]]. The development of the MV-series was documented in [[Tracy Kidder]]'s popular 1981 book, ''[[The Soul of a New Machine]]''. Data General itself would later evolve into a vendor of Intel processor-based servers and storage arrays, eventually being purchased by [[Dell EMC|EMC]]. | Data General followed up on the success of the original Nova with a series of faster designs. The Eclipse family of systems was later introduced with an extended upwardly compatible instruction set, and the MV-series further extended the Eclipse into a 32-bit architecture to compete with the DEC [[VAX]]. The development of the MV-series was documented in [[Tracy Kidder]]'s popular 1981 book, ''[[The Soul of a New Machine]]''. Data General itself would later evolve into a vendor of Intel processor-based servers and storage arrays, eventually being purchased by [[Dell EMC|EMC]]. | ||
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All arithmetic instructions operated between accumulators. For operations requiring two operands, one was taken from the source accumulator, and one from the destination accumulator, and the result was deposited in the destination accumulator. For single-operand operations, the operand was taken from the source register and the result replaced the destination register. For all single-operand opcodes, it was permissible for the source and destination accumulators to be the same, and the operation functioned as expected. | All arithmetic instructions operated between accumulators. For operations requiring two operands, one was taken from the source accumulator, and one from the destination accumulator, and the result was deposited in the destination accumulator. For single-operand operations, the operand was taken from the source register and the result replaced the destination register. For all single-operand opcodes, it was permissible for the source and destination accumulators to be the same, and the operation functioned as expected. | ||
All arithmetic instructions included a "no-load" bit which, when set, suppressed the transfer of the result to the destination register; this was used in conjunction with the test options to perform a test without losing the existing contents of the destination register. In assembly language, adding a '#' to the opcode set the no-load bit. | All arithmetic instructions included a "no-load" bit which, when set, suppressed the transfer of the result to the destination register; this was used in conjunction with the test options to perform a test without losing the existing contents of the destination register. In [[assembly language]], adding a '#' to the opcode set the no-load bit. | ||
The CPU contained a single-bit register called the carry bit, which after an arithmetic operation would contain the carry out of the most significant bit. The carry bit could be set to a desired value prior to performing the operation using a two-bit field in the instruction. The bit could be set, cleared, or complemented prior to performing the instruction. In assembly language, these options were specified by adding a letter to the opcode: 'O' — set the carry bit; 'Z' — clear the carry bit, 'C' — complement the carry bit, nothing — leave the carry bit alone. If the no-load bit was also specified, the specified carry value would be used for the computation, but the actual carry register would remain unaltered. | The CPU contained a single-bit register called the carry bit, which after an arithmetic operation would contain the carry out of the most significant bit. The carry bit could be set to a desired value prior to performing the operation using a two-bit field in the instruction. The bit could be set, cleared, or complemented prior to performing the instruction. In assembly language, these options were specified by adding a letter to the opcode: 'O' — set the carry bit; 'Z' — clear the carry bit, 'C' — complement the carry bit, nothing — leave the carry bit alone. If the no-load bit was also specified, the specified carry value would be used for the computation, but the actual carry register would remain unaltered. | ||
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{{sxhl|2=nasm|JSR@ 0,17}} | {{sxhl|2=nasm|JSR@ 0,17}} | ||
Jump indirect to the memory address specified by the contents of location 17, in page zero space, and deposit the return address in accumulator 3. This was the standard method for making an RDOS system call on early Nova models; the assembly language mnemonic {{code|.SYSTM}} translated to this. | Jump indirect to the memory address specified by the contents of location 17, in page zero space, and deposit the return address in accumulator 3. This was the standard method for making an RDOS [[system call]] on early Nova models; the assembly language mnemonic {{code|.SYSTM}} translated to this. | ||
{{sxhl|2=nasm|JMP 0,3}} | {{sxhl|2=nasm|JMP 0,3}} | ||
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* {{code|SKPDZ}} — skip the next instruction if the device's done flag is clear | * {{code|SKPDZ}} — skip the next instruction if the device's done flag is clear | ||
Starting a device caused it to set its busy flag. When the requested operation was completed, conventionally the device cleared its busy flag and set its done flag; most devices had their interrupt request mechanism wired to the done flag, so setting the done flag caused an interrupt (if interrupts were enabled and the device wasn't masked). | Starting a device caused it to set its busy flag. When the requested operation was completed, conventionally the device cleared its busy flag and set its done flag; most devices had their [[interrupt request]] mechanism wired to the done flag, so setting the done flag caused an interrupt (if interrupts were enabled and the device wasn't masked). | ||
====Special instructions==== | ====Special instructions==== | ||
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From the hardware standpoint, the interrupt mechanism was relatively simple, but also less flexible, than current CPU architectures. The backplane supported a single interrupt request line, which all devices capable of interrupting connected to. When a device needed to request an interrupt, it raised this line. The CPU took the interrupt as soon as it completed the current instruction. As stated above, a device was expected to raise its "done" I/O flag when it requested an interrupt, and the convention was that the device would clear its interrupt request when the CPU executed a I/O clear instruction on the device's channel number. | From the hardware standpoint, the interrupt mechanism was relatively simple, but also less flexible, than current CPU architectures. The backplane supported a single interrupt request line, which all devices capable of interrupting connected to. When a device needed to request an interrupt, it raised this line. The CPU took the interrupt as soon as it completed the current instruction. As stated above, a device was expected to raise its "done" I/O flag when it requested an interrupt, and the convention was that the device would clear its interrupt request when the CPU executed a I/O clear instruction on the device's channel number. | ||
The CPU expected the operating system to place the address of its interrupt service routine into memory address 1. When a device interrupted, the CPU did an indirect jump through address 1, placing the return address into memory address 0, and disabling further interrupts. The interrupt handler would then perform an {{code|INTA}} instruction to discover the channel number of the interrupting device. This worked by raising an "acknowledge" signal on the backplane. The acknowledge signal was wired in a daisy-chain format across the backplane, such that it looped through each board on the bus. Any device requesting an interrupt was expected to block the further propagation of the acknowledge signal down the bus, so that if two or more devices had pending interrupts simultaneously, only the first one would see the acknowledge signal. That device then responded by placing its channel number on the data lines on the bus. This meant that, in the case of simultaneous interrupt requests, the device that had priority was determined by which one was physically closest to the CPU in the card cage. | The CPU expected the operating system to place the address of its interrupt service routine into memory address 1. When a device interrupted, the CPU did an indirect jump through address 1, placing the return address into memory address 0, and disabling further interrupts. The [[interrupt handler]] would then perform an {{code|INTA}} instruction to discover the channel number of the interrupting device. This worked by raising an "acknowledge" signal on the backplane. The acknowledge signal was wired in a daisy-chain format across the backplane, such that it looped through each board on the bus. Any device requesting an interrupt was expected to block the further propagation of the acknowledge signal down the bus, so that if two or more devices had pending interrupts simultaneously, only the first one would see the acknowledge signal. That device then responded by placing its channel number on the data lines on the bus. This meant that, in the case of simultaneous interrupt requests, the device that had priority was determined by which one was physically closest to the CPU in the card cage. | ||
The operating system's interrupt service routine then typically performed an indexed jump using the received channel number, to jump to the specific interrupt handling routine for the device. There were a few devices, notably the CPU's power-failure detection circuit, which did not respond to the {{code|INTA}} instruction. If the {{code|INTA}} returned a result of zero, the interrupt service routine had to poll all of the non-INTA-responding devices using the {{code|SKPDZ}}/{{code|SKPDN}} instructions to see which one interrupted. | The operating system's interrupt service routine then typically performed an indexed jump using the received channel number, to jump to the specific interrupt handling routine for the device. There were a few devices, notably the CPU's power-failure detection circuit, which did not respond to the {{code|INTA}} instruction. If the {{code|INTA}} returned a result of zero, the interrupt service routine had to poll all of the non-INTA-responding devices using the {{code|SKPDZ}}/{{code|SKPDN}} instructions to see which one interrupted. | ||