Central processing unit: Difference between revisions
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[[File:Intel_i9-14900KF_CPU.jpg|thumb|A | [[File:Intel_i9-14900KF_CPU.jpg|thumb|A high-end consumer CPU made by [[Intel]]: an [[Intel Core i9-14900KF]]]] | ||
[[File:Intel Xeon 3060 Conroe (Reshoot) - Flickr - cole8888.jpg|thumb|280px|upright=1.5|Inside a central processing unit: The [[integrated circuit]] of Intel's [[List of Intel Xeon processors (Core-based)#ark27205|Xeon 3060]], first manufactured in 2006]] | [[File:Intel Xeon 3060 Conroe (Reshoot) - Flickr - cole8888.jpg|thumb|280px|upright=1.5|Inside a central processing unit: The [[integrated circuit]] of Intel's [[List of Intel Xeon processors (Core-based)#ark27205|Xeon 3060]], first manufactured in 2006]] | ||
A '''central processing unit''' ('''CPU'''), also | A '''central processing unit''' ('''CPU'''), also known as a '''central processor''', '''main processor''', or simply '''processor''', is the primary [[Processor (computing)|processor]] in a given [[computer]].<ref>{{Cite book |last=Team |first=YCT Expert |url=https://books.google.com/books?id=O_fZEAAAQBAJ&dq=A+central+processing+unit+(CPU)%E2%80%94also+called+a+central+processor+or+main+processor%E2%80%94is+the+most+important+processor+in+a+given+computer.&pg=PA425 |title=Engineering Drawing & Basic Science |publisher=Youth Competition Times |pages=425 |language=en}}</ref><ref>{{Cite book |last=Nagpal |first=D. P. |url=https://books.google.com/books?id=LAsbEAAAQBAJ&dq=A+central+processing+unit+(CPU)%E2%80%94also+called+a+central+processor+or+main+processor%E2%80%94is+the+most+important+processor+in+a+given+computer.&pg=PA33 |title=Computer Fundamentals |date=2008 |publisher=S. Chand Publishing |isbn=978-81-219-2388-0 |pages=33 |language=en}}</ref> Its [[electronic circuit]]ry executes [[Instruction (computing)|instructions]] of a [[computer program]], such as [[arithmetic]], logic, controlling, and [[input/output]] (I/O) operations.<ref>{{Cite web |title=What is processor (CPU)? A definition from WhatIs.com |date=14 August 2019|publisher=Informa TechTarget|url=https://www.techtarget.com/whatis/definition/processor |access-date=2024-03-15 |website=WhatIs |language=en}}</ref><ref>{{Cite book |last=Chesalov |first=Alexander |url=https://books.google.com/books?id=VlG5EAAAQBAJ&dq=cpu+electronic+circuitry+executes+instructions+of+a+computer+program,+such+as+arithmetic,+logic,+controlling,+and+input/output+(I/O)+operations&pg=PT54 |title=The fourth industrial revolution glossarium: over 1500 of the hottest terms you will use to create the future |date=2023-04-12 |publisher=Litres |isbn=978-5-04-541163-9 |language=en}}</ref><ref>{{Cite book |last=Jagare |first=Ulrika |url=https://books.google.com/books?id=ZwxsEAAAQBAJ&dq=cpu+electronic+circuitry+executes+instructions+of+a+computer+program,+such+as+arithmetic,+logic,+controlling,+and+input/output+(I/O)+operations&pg=PT91 |title=Operating AI: Bridging the Gap Between Technology and Business |date=2022-04-19 |publisher=John Wiley & Sons |isbn=978-1-119-83321-5 |language=en}}</ref> This role contrasts with that of external components, such as [[main memory]] and I/O circuitry,<ref name="kuck">{{cite book|last1= Kuck|first1= David|title= Computers and Computations, Vol 1|date= 1978|publisher= John Wiley & Sons, Inc.|isbn= 978-0471027164|page= 12}}</ref> and specialized [[coprocessor]]s such as [[graphics processing unit]]s (GPUs). | ||
The form, [[CPU design|design]], and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged.<ref>{{Cite book |last=Prabhat |first=Team |url=https://books.google.com/books?id=sbqcEAAAQBAJ&dq=design,+and+implementation+of+CPUs+have+changed+over+time,+but+their+fundamental+operation+remains+almost+unchanged.&pg=PA95 |title=Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English: Bestseller Book by Team Prabhat: Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English |date=2023-04-13 |publisher=Prabhat Prakashan |isbn=978-93-5488-527-3 |pages=95 |language=en}}</ref> Principal components of a CPU include the [[arithmetic–logic unit]] (ALU) that performs [[arithmetic operation|arithmetic]] and [[Bitwise operation|logic operations]], [[processor register]]s that supply [[operand]]s to the ALU and store the results of ALU operations, and a [[control unit]] that orchestrates the [[#Fetch|fetching (from memory)]], [[#Decode|decoding]] and [[#Execute|execution (of instructions)]] by directing the coordinated operations of the ALU, registers, and other components. Modern CPUs devote a lot of semiconductor area to [[Cache (computing)|caches]] and [[instruction-level parallelism]] to increase performance and to [[CPU modes]] to support [[operating system]]s and [[virtualization]]. | The form, [[CPU design|design]], and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged.<ref>{{Cite book |last=Prabhat |first=Team |url=https://books.google.com/books?id=sbqcEAAAQBAJ&dq=design,+and+implementation+of+CPUs+have+changed+over+time,+but+their+fundamental+operation+remains+almost+unchanged.&pg=PA95 |title=Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English: Bestseller Book by Team Prabhat: Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English |date=2023-04-13 |publisher=Prabhat Prakashan |isbn=978-93-5488-527-3 |pages=95 |language=en}}</ref> Principal components of a CPU include the [[Arithmetic logic unit|arithmetic–logic unit]] (ALU) that performs [[arithmetic operation|arithmetic]] and [[Bitwise operation|logic operations]], [[processor register]]s that supply [[operand]]s to the ALU and store the results of ALU operations, and a [[control unit]] that orchestrates the [[#Fetch|fetching (from memory)]], [[#Decode|decoding]] and [[#Execute|execution (of instructions)]] by directing the coordinated operations of the ALU, registers, and other components. Modern CPUs devote a lot of semiconductor area to [[Cache (computing)|caches]] and [[instruction-level parallelism]] to increase performance and to [[CPU modes]] to support [[operating system]]s and [[virtualization]]. | ||
Most modern CPUs are implemented on [[integrated circuit]] (IC) [[microprocessor]]s, with one or more CPUs on a single IC chip. Microprocessor chips with multiple CPUs are called ''[[multi-core processor]]s''.<ref>{{Cite web |title=What is a multicore processor and how does it work? |url=https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |access-date=2024-03-15 |website=Data Center |language=en}}</ref> The individual physical CPUs, called | Most modern CPUs are implemented on [[integrated circuit]] (IC) [[microprocessor]]s, with one or more CPUs on a single IC chip. Microprocessor chips with multiple CPUs are called ''[[multi-core processor]]s'' (''MCPs'').<ref>{{Cite web |title=What is a multicore processor and how does it work? |url=https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |access-date=2024-03-15 |website=Data Center |language=en}}</ref> The individual physical CPUs, called ''processor cores'', can also be [[Multithreading (computer architecture)|multithreaded]] to support CPU-level multithreading.<ref name="intel-pcm" /> | ||
An IC that contains a CPU may also contain [[Computer memory|memory]], [[peripheral]] interfaces, and other components of a computer;<ref>{{Cite book |last=Herres |first=David |url=https://books.google.com/books?id=RYoBEAAAQBAJ&dq=An+IC+that+contains+a+CPU+may+also+contain+memory&pg=PA130 |title=Oscilloscopes: A Manual for Students, Engineers, and Scientists |date=2020-10-06 |publisher=Springer Nature |isbn=978-3-030-53885-9 |pages=130 |language=en}}</ref> such integrated devices are variously called [[microcontroller]]s or [[ | An IC that contains a CPU may also contain [[Computer memory|memory]], [[peripheral]] interfaces, and other components of a computer;<ref>{{Cite book |last=Herres |first=David |url=https://books.google.com/books?id=RYoBEAAAQBAJ&dq=An+IC+that+contains+a+CPU+may+also+contain+memory&pg=PA130 |title=Oscilloscopes: A Manual for Students, Engineers, and Scientists |date=2020-10-06 |publisher=Springer Nature |isbn=978-3-030-53885-9 |pages=130 |language=en}}</ref> such integrated devices are variously called [[microcontroller]]s or [[systems on chip]] (SoCs). | ||
==History== | ==History== | ||
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Early CPUs were custom designs used as part of a larger and sometimes distinctive computer.<ref>{{cite web|title=The First Generation|url=http://www.computerhistory.org/revolution/birth-of-the-computer/4/92|publisher=Computer History Museum|access-date=September 29, 2015|archive-date=November 22, 2016|archive-url=https://web.archive.org/web/20161122064835/http://www.computerhistory.org/revolution/birth-of-the-computer/4/92|url-status=live}}</ref> However, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete [[transistor]] [[Mainframe computer|mainframes]] and [[minicomputer]]s, and has rapidly accelerated with the popularization of the [[integrated circuit]] (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of [[Nanometre|nanometers]].<ref name="nobel">{{cite web|title=The History of the Integrated Circuit|url=https://educationalgames.nobelprize.org/educational/physics/integrated_circuit/history/index.html|website=Nobelprize.org|access-date=July 17, 2022|archive-date=May 22, 2022|archive-url=https://web.archive.org/web/20220522104138/https://educationalgames.nobelprize.org/educational/physics/integrated_circuit/history/index.html|url-status=live}}</ref> Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles<ref>{{cite web|last1=Turley|first1=Jim|title=Motoring with microprocessors|date=11 August 2003|url=https://www.embedded.com/motoring-with-microprocessors/|publisher=Embedded|access-date=December 26, 2022|archive-date=14 October 2022|archive-url=https://web.archive.org/web/20221014214157/https://www.embedded.com/motoring-with-microprocessors/|url-status=live}}</ref> to cellphones,<ref>{{cite web|title=Mobile Processor Guide – Summer 2013|url=http://www.androidauthority.com/mobile-processor-guide-summer-2013-234354/|publisher=Android Authority|access-date=November 15, 2015|date=2013-06-25|archive-date=2015-11-17|archive-url=https://web.archive.org/web/20151117034027/http://www.androidauthority.com/mobile-processor-guide-summer-2013-234354/|url-status=live}}</ref> and sometimes even in toys.<ref>{{cite web |title=Section 250: Microprocessors and Toys: An Introduction to Computing Systems |url=https://eng100.engin.umich.edu/list/sec250/ |publisher=The University of Michigan |access-date=October 9, 2018 |archive-date=April 13, 2021 |archive-url=https://web.archive.org/web/20210413194655/https://eng100.engin.umich.edu/list/sec250/ |url-status=dead }}</ref><ref>{{cite web|title=ARM946 Processor |url=https://www.arm.com/products/processors/classic/arm9/arm946.php|publisher=ARM|url-status=dead|archive-url = https://web.archive.org/web/20151117015143/https://www.arm.com/products/processors/classic/arm9/arm946.php|archive-date = 17 November 2015}}</ref> | Early CPUs were custom designs used as part of a larger and sometimes distinctive computer.<ref>{{cite web|title=The First Generation|url=http://www.computerhistory.org/revolution/birth-of-the-computer/4/92|publisher=Computer History Museum|access-date=September 29, 2015|archive-date=November 22, 2016|archive-url=https://web.archive.org/web/20161122064835/http://www.computerhistory.org/revolution/birth-of-the-computer/4/92|url-status=live}}</ref> However, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete [[transistor]] [[Mainframe computer|mainframes]] and [[minicomputer]]s, and has rapidly accelerated with the popularization of the [[integrated circuit]] (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of [[Nanometre|nanometers]].<ref name="nobel">{{cite web|title=The History of the Integrated Circuit|url=https://educationalgames.nobelprize.org/educational/physics/integrated_circuit/history/index.html|website=Nobelprize.org|access-date=July 17, 2022|archive-date=May 22, 2022|archive-url=https://web.archive.org/web/20220522104138/https://educationalgames.nobelprize.org/educational/physics/integrated_circuit/history/index.html|url-status=live}}</ref> Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles<ref>{{cite web|last1=Turley|first1=Jim|title=Motoring with microprocessors|date=11 August 2003|url=https://www.embedded.com/motoring-with-microprocessors/|publisher=Embedded|access-date=December 26, 2022|archive-date=14 October 2022|archive-url=https://web.archive.org/web/20221014214157/https://www.embedded.com/motoring-with-microprocessors/|url-status=live}}</ref> to cellphones,<ref>{{cite web|title=Mobile Processor Guide – Summer 2013|url=http://www.androidauthority.com/mobile-processor-guide-summer-2013-234354/|publisher=Android Authority|access-date=November 15, 2015|date=2013-06-25|archive-date=2015-11-17|archive-url=https://web.archive.org/web/20151117034027/http://www.androidauthority.com/mobile-processor-guide-summer-2013-234354/|url-status=live}}</ref> and sometimes even in toys.<ref>{{cite web |title=Section 250: Microprocessors and Toys: An Introduction to Computing Systems |url=https://eng100.engin.umich.edu/list/sec250/ |publisher=The University of Michigan |access-date=October 9, 2018 |archive-date=April 13, 2021 |archive-url=https://web.archive.org/web/20210413194655/https://eng100.engin.umich.edu/list/sec250/ |url-status=dead }}</ref><ref>{{cite web|title=ARM946 Processor |url=https://www.arm.com/products/processors/classic/arm9/arm946.php|publisher=ARM|url-status=dead|archive-url = https://web.archive.org/web/20151117015143/https://www.arm.com/products/processors/classic/arm9/arm946.php|archive-date = 17 November 2015}}</ref> | ||
While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, and the design became known as the [[von Neumann architecture]], others before him, such as [[Konrad Zuse]], had suggested and implemented similar ideas.<ref>{{cite web|title=Konrad Zuse|url= | While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, and the design became known as the [[von Neumann architecture]], others before him, such as [[Konrad Zuse]], had suggested and implemented similar ideas.<ref>{{cite web |title=Konrad Zuse |date=18 August 2025 |url=https://computerhistory.org/profile/konrad-zuse/ |publisher=Computer History Museum |access-date=September 26, 2025}}</ref> The so-called [[Harvard architecture]] of the [[Harvard Mark I]], which was completed before EDVAC,<ref>{{cite web|title=Timeline of Computer History: Computers|url=https://www.computerhistory.org/timeline/computers/|publisher=Computer History Museum|access-date=November 21, 2015|archive-date=December 29, 2017|archive-url=https://web.archive.org/web/20171229052342/http://www.computerhistory.org/timeline/computers/|url-status=live}}</ref><ref>{{cite web |last=White |first=Stephen |title=A Brief History of Computing – First Generation Computers |url=http://trillian.randomstuff.org.uk/~stephen/history/timeline-GEN1.html |url-status=live |archive-url=https://web.archive.org/web/20180102205958/http://trillian.randomstuff.org.uk/~stephen/history/timeline-GEN1.html |archive-date=January 2, 2018 |access-date=November 21, 2015}}</ref> also used a stored-program design using [[Punched tape|punched paper tape]] rather than electronic memory.<ref>{{cite web |title=Harvard University Mark I Paper Tape Punch Unit |url=https://www.computerhistory.org/collections/catalog/102698407 |url-status=live |archive-url=https://web.archive.org/web/20151122011934/http://www.computerhistory.org/collections/catalog/102698407 |archive-date=November 22, 2015 |access-date=November 21, 2015 |publisher=Computer History Museum}}</ref> The key difference between the two is that Harvard architecture separates the storage and treatment of CPU instructions and data, whereas von Neumann architecture uses the same memory space for both.<ref>{{cite web|title=What is the difference between a von Neumann architecture and a Harvard architecture?|url=http://infocenter.arm.com/help/index.jsp?topic=%2Fcom.arm.doc.faqs%2F3738.html|publisher=ARM|access-date=November 22, 2015|archive-date=November 18, 2015|archive-url=https://web.archive.org/web/20151118200529/http://infocenter.arm.com/help/index.jsp?topic=%2Fcom.arm.doc.faqs%2F3738.html|url-status=live}}</ref> Most modern CPUs are primarily von Neumann in design, but CPUs with the Harvard architecture are seen as well, especially in embedded applications; for instance, the [[Atmel AVR]] microcontrollers are Harvard-architecture processors.<ref>{{cite web|title=Advanced Architecture Optimizes the Atmel AVR CPU|url=http://www.atmel.com/technologies/cpu_core/avr.aspx|publisher=Atmel|access-date=November 22, 2015|archive-date=November 14, 2015|archive-url=https://web.archive.org/web/20151114090428/http://www.atmel.com/technologies/cpu_core/avr.aspx|url-status=dead}}</ref> | ||
[[ | Prior to the invention of the transistor, [[relay]]s and [[vacuum tube]]s (thermionic tubes) were commonly used as switching elements;<ref>{{cite web|title=Switches, transistors and relays|url=http://www.bbc.co.uk/schools/gcsebitesize/design/electronics/switchesrev5.shtml|publisher=BBC |url-status=dead|archive-url = https://web.archive.org/web/20161205142752/http://www.bbc.co.uk/schools/gcsebitesize/design/electronics/switchesrev5.shtml|archive-date = 5 December 2016}}</ref><ref>{{cite web|title=Introducing the Vacuum Transistor: A Device Made of Nothing|url=https://spectrum.ieee.org/introducing-the-vacuum-transistor-a-device-made-of-nothing|website=IEEE Spectrum|access-date=27 January 2019|date=2014-06-23|archive-date=2018-03-23|archive-url=https://web.archive.org/web/20180323183612/https://spectrum.ieee.org/semiconductors/devices/introducing-the-vacuum-transistor-a-device-made-of-nothing|url-status=live}}</ref> a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches. [[Vacuum-tube computer]]s such as EDVAC tended to average eight hours between failures, whereas relay computers—such as the slower but earlier [[Harvard Mark I]]—failed very rarely.<ref name="weik1961" /> In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low [[clock rate]]s compared to modern microelectronic designs. Clock signal frequencies ranging from 100 [[Hertz|kHz]] to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.<ref>{{cite book|title=What Is Computer Performance?|url=http://www.nap.edu/read/12980/chapter/5#55|publisher=The National Academies Press|access-date=May 16, 2016|doi=10.17226/12980|year=2011|isbn=978-0-309-15951-7|archive-date=June 5, 2016|archive-url=https://web.archive.org/web/20160605083842/http://www.nap.edu/read/12980/chapter/5#55|url-status=live}}</ref> | ||
===Transistor CPUs=== | ===Transistor CPUs=== | ||
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The design complexity of CPUs increased as various technologies facilitated the building of smaller and more reliable electronic devices. The first such improvement came with the advent of the [[transistor]]. Transistorized CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable, and fragile switching elements, like [[vacuum tube]]s and [[relay]]s.<ref>{{cite web|title=1953: Transistorized Computers Emerge|url=http://www.computerhistory.org/siliconengine/transistorized-computers-emerge/|work=Computer History Museum|access-date=June 3, 2016|archive-date=June 1, 2016|archive-url=https://web.archive.org/web/20160601191253/http://www.computerhistory.org/siliconengine/transistorized-computers-emerge/|url-status=live}}</ref> With this improvement, more complex and reliable CPUs were built onto one or several [[printed circuit board]]s containing discrete (individual) components. | The design complexity of CPUs increased as various technologies facilitated the building of smaller and more reliable electronic devices. The first such improvement came with the advent of the [[transistor]]. Transistorized CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable, and fragile switching elements, like [[vacuum tube]]s and [[relay]]s.<ref>{{cite web|title=1953: Transistorized Computers Emerge|url=http://www.computerhistory.org/siliconengine/transistorized-computers-emerge/|work=Computer History Museum|access-date=June 3, 2016|archive-date=June 1, 2016|archive-url=https://web.archive.org/web/20160601191253/http://www.computerhistory.org/siliconengine/transistorized-computers-emerge/|url-status=live}}</ref> With this improvement, more complex and reliable CPUs were built onto one or several [[printed circuit board]]s containing discrete (individual) components. | ||
In 1964, [[IBM]] introduced its [[IBM System/360]] computer architecture that was used in a series of computers capable of running the same programs with different speeds and performances.<ref>{{cite web|url=http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS360.html|title=IBM System/360 Dates and Characteristics|publisher=IBM|date=2003-01-23|access-date=2016-01-13|archive-date=2017-11-21|archive-url=https://web.archive.org/web/20171121223500/http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS360.html|url-status=dead}}</ref> This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM used the concept of a [[microprogram]] (often called "microcode"), which still sees widespread use in modern CPUs.<ref name="amdahl1964">{{cite journal | last1 = Amdahl | first1 = G. M. | author-link1 = Gene Amdahl | last2 = Blaauw | first2 = G. A. | author-link2 = Gerrit Blaauw | last3 = Brooks | first3 = F. P. Jr. | author-link3 = Fred Brooks | title = Architecture of the IBM System/360 | journal = IBM Journal of Research and Development | volume = 8 | issue = 2 | pages = 87–101 | issn = 0018-8646 | publisher = [[IBM]] | date = April 1964 | doi = 10.1147/rd.82.0087 }}</ref> The System/360 architecture was so popular that it dominated the [[mainframe computer]] market for decades and left a legacy that is continued by similar modern computers like the IBM [[IBM System z|zSeries]].<ref>{{cite web|last1=Brodkin|first1=John|title=50 years ago, IBM created mainframe that helped send men to the Moon|url=https://arstechnica.com/information-technology/2014/04/50-years-ago-ibm-created-mainframe-that-helped-bring-men-to-the-moon/|website=Ars Technica|date=7 April 2014|access-date=9 April 2016|archive-date=8 April 2016|archive-url=https://web.archive.org/web/20160408105602/http://arstechnica.com/information-technology/2014/04/50-years-ago-ibm-created-mainframe-that-helped-bring-men-to-the-moon/|url-status=live}}</ref><ref>{{cite web|last1=Clarke|first1=Gavin|title=Why won't you DIE? IBM's S/360 and its legacy at 50|url=https://www.theregister. | In 1964, [[IBM]] introduced its [[IBM System/360]] computer architecture that was used in a series of computers capable of running the same programs with different speeds and performances.<ref>{{cite web|url=http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS360.html|title=IBM System/360 Dates and Characteristics|publisher=IBM|date=2003-01-23|access-date=2016-01-13|archive-date=2017-11-21|archive-url=https://web.archive.org/web/20171121223500/http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS360.html|url-status=dead}}</ref> This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM used the concept of a [[microprogram]] (often called "microcode"), which still sees widespread use in modern CPUs.<ref name="amdahl1964">{{cite journal | last1 = Amdahl | first1 = G. M. | author-link1 = Gene Amdahl | last2 = Blaauw | first2 = G. A. | author-link2 = Gerrit Blaauw | last3 = Brooks | first3 = F. P. Jr. | author-link3 = Fred Brooks | title = Architecture of the IBM System/360 | journal = IBM Journal of Research and Development | volume = 8 | issue = 2 | pages = 87–101 | issn = 0018-8646 | publisher = [[IBM]] | date = April 1964 | doi = 10.1147/rd.82.0087 }}</ref> The System/360 architecture was so popular that it dominated the [[mainframe computer]] market for decades and left a legacy that is continued by similar modern computers like the IBM [[IBM System z|zSeries]].<ref>{{cite web|last1=Brodkin|first1=John|title=50 years ago, IBM created mainframe that helped send men to the Moon|url=https://arstechnica.com/information-technology/2014/04/50-years-ago-ibm-created-mainframe-that-helped-bring-men-to-the-moon/|website=Ars Technica|date=7 April 2014|access-date=9 April 2016|archive-date=8 April 2016|archive-url=https://web.archive.org/web/20160408105602/http://arstechnica.com/information-technology/2014/04/50-years-ago-ibm-created-mainframe-that-helped-bring-men-to-the-moon/|url-status=live}}</ref><ref>{{cite web |last1=Clarke |first1=Gavin |title=Why won't you DIE? IBM's S/360 and its legacy at 50 |url=https://www.theregister.com/2014/04/07/ibm_s_360_50_anniversary/ |website=The Register |access-date=26 September 2025}}</ref> In 1965, [[Digital Equipment Corporation]] (DEC) introduced another influential computer aimed at the scientific and research markets—the [[PDP-8]].<ref>{{cite web|title=Online PDP-8 Home Page, Run a PDP-8|url=http://www.pdp8.net/index.shtml|website=PDP8|access-date=September 25, 2015|archive-date=August 11, 2015|archive-url=https://web.archive.org/web/20150811174442/http://www.pdp8.net/index.shtml|url-status=live}}</ref> | ||
[[File:Board with SPARC64 VIIIfx processors on display in Fujitsu HQ.JPG|thumb|Fujitsu board with SPARC64 VIIIfx processors]] | [[File:Board with SPARC64 VIIIfx processors on display in Fujitsu HQ.JPG|thumb|Fujitsu board with SPARC64 VIIIfx processors]] | ||
Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in comparison to a tube or relay.<ref>{{cite web|title=Transistors, Relays, and Controlling High-Current Loads|url=https://itp.nyu.edu/physcomp/lessons/electronics/transistors-relays-and-controlling-high-current-loads/|publisher=ITP Physical Computing|work=New York University|access-date=9 April 2016|archive-date=21 April 2016|archive-url=https://web.archive.org/web/20160421232136/https://itp.nyu.edu/physcomp/lessons/electronics/transistors-relays-and-controlling-high-current-loads/|url-status=live}}</ref> The increased reliability and dramatically increased speed of the switching elements, which were almost exclusively transistors by this time; CPU clock rates in the tens of megahertz were easily obtained during this period.<ref name = pcgamer>{{cite magazine|last1=Lilly|first1=Paul|title=A Brief History of CPUs: 31 Awesome Years of x86|url=http://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/|magazine=PC Gamer|access-date=June 15, 2016|date=2009-04-14|archive-date=2016-06-13|archive-url=https://web.archive.org/web/20160613202439/http://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/|url-status=live}}</ref> Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like [[single instruction, multiple data]] (SIMD) [[vector processor]]s began to appear.<ref name="patterson">{{cite book |last1=Patterson |first1=David A. |url=https://archive.org/details/computerorganiz000henn/page/751 |title=Computer Organization and Design: the Hardware/Software Interface |last2=Hennessy |first2=John L. |last3=Larus |first3=James R. |date=1999 |publisher=Kaufmann |isbn=978-1558604285 |edition=3rd printing of 2nd |location=San Francisco, California |page=[https://archive.org/details/computerorganiz000henn/page/751 751] |language=en-us}}</ref> These early experimental designs later gave rise to the era of specialized [[supercomputer]]s like those made by [[Cray|Cray Inc]] and [[Fujitsu|Fujitsu Ltd]].<ref name="patterson"/> | Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in comparison to a tube or relay.<ref>{{cite web|title=Transistors, Relays, and Controlling High-Current Loads|url=https://itp.nyu.edu/physcomp/lessons/electronics/transistors-relays-and-controlling-high-current-loads/|publisher=ITP Physical Computing|work=New York University|access-date=9 April 2016|archive-date=21 April 2016|archive-url=https://web.archive.org/web/20160421232136/https://itp.nyu.edu/physcomp/lessons/electronics/transistors-relays-and-controlling-high-current-loads/|url-status=live}}</ref> The increased reliability and dramatically increased speed of the switching elements, which were almost exclusively transistors by this time; CPU clock rates in the tens of megahertz were easily obtained during this period.<ref name = pcgamer>{{cite magazine|last1=Lilly|first1=Paul|title=A Brief History of CPUs: 31 Awesome Years of x86|url=http://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/|magazine=PC Gamer|access-date=June 15, 2016|date=2009-04-14|archive-date=2016-06-13|archive-url=https://web.archive.org/web/20160613202439/http://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/|url-status=live}}</ref> Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like [[single instruction, multiple data]] (SIMD) [[vector processor]]s began to appear.<ref name="patterson">{{cite book |last1=Patterson |first1=David A. |url=https://archive.org/details/computerorganiz000henn/page/751 |title=Computer Organization and Design: the Hardware/Software Interface |last2=Hennessy |first2=John L. |last3=Larus |first3=James R. |date=1999 |publisher=Kaufmann |isbn=978-1558604285 |edition=3rd printing of 2nd |location=San Francisco, California |page=[https://archive.org/details/computerorganiz000henn/page/751 751] |language=en-us}}</ref> These early experimental designs later gave rise to the era of specialized [[supercomputer]]s like those made by [[Cray|Cray Inc]] and [[Fujitsu|Fujitsu Ltd]].<ref name="patterson"/> | ||
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===Large-scale integration CPUs=== | ===Large-scale integration CPUs=== | ||
[[Lee Boysel]] published influential articles, including a 1967 "manifesto", which described how to build the equivalent of a 32-bit mainframe computer from a relatively small number of [[large-scale integration]] circuits (LSI).<ref>{{cite book |author=Bassett |first=Ross Knox |url=https://books.google.com/books?id=UUbB3d2UnaAC |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |publisher=[[The Johns Hopkins University Press]] |year=2007 |isbn=978-0-8018-6809-2 |pages=127–128, 256, and 314 |language=en-us}}</ref><ref name="shirriff">{{cite web |first=Ken |last=Shirriff | [[Lee Boysel]] published influential articles, including a 1967 "manifesto", which described how to build the equivalent of a 32-bit mainframe computer from a relatively small number of [[large-scale integration]] circuits (LSI).<ref>{{cite book |author=Bassett |first=Ross Knox |url=https://books.google.com/books?id=UUbB3d2UnaAC |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |publisher=[[The Johns Hopkins University Press]] |year=2007 |isbn=978-0-8018-6809-2 |pages=127–128, 256, and 314 |language=en-us}}</ref><ref name="shirriff">{{cite web |first=Ken |last=Shirriff | ||
|url=http://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |title=The Texas Instruments TMX 1795: the first, forgotten microprocessor |archive-url=https://web.archive.org/web/20210126074942/http://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |archive-date=2021-01-26 |url-status=live}}</ref> The only way to build LSI chips, which are chips with a hundred or more gates, was to build them using a [[MOSFET|metal–oxide–semiconductor]] (MOS) [[semiconductor manufacturing process]] (either [[PMOS logic]], [[NMOS logic]], or [[CMOS]] logic). However, some companies continued to build processors out of bipolar [[transistor–transistor logic]] (TTL) chips because bipolar junction transistors were faster than MOS chips up until the 1970s (a few companies such as [[Datapoint]] continued to build processors out of TTL chips until the early 1980s).<ref name="shirriff" /> In the 1960s, MOS ICs were slower and initially considered useful only in applications that required low power.<ref>{{cite web|url= | |url=http://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |title=The Texas Instruments TMX 1795: the first, forgotten microprocessor |archive-url=https://web.archive.org/web/20210126074942/http://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |archive-date=2021-01-26 |url-status=live}}</ref> The only way to build LSI chips, which are chips with a hundred or more gates, was to build them using a [[MOSFET|metal–oxide–semiconductor]] (MOS) [[semiconductor manufacturing process]] (either [[PMOS logic]], [[NMOS logic]], or [[CMOS]] logic). However, some companies continued to build processors out of bipolar [[transistor–transistor logic]] (TTL) chips because bipolar junction transistors were faster than MOS chips up until the 1970s (a few companies such as [[Datapoint]] continued to build processors out of TTL chips until the early 1980s).<ref name="shirriff" /> In the 1960s, MOS ICs were slower and initially considered useful only in applications that required low power.<ref>{{cite web|url=https://www.brown.edu/Departments/Engineering/Labs/ddzo/speed.html|title=Speed & Power in Logic Families|access-date=2017-08-02|archive-date=2017-07-26|archive-url=https://web.archive.org/web/20170726175011/http://www.brown.edu/Departments/Engineering/Labs/ddzo/speed.html|url-status=live}}.</ref><ref>{{cite book |first=T. J. |last=Stonham |url=https://books.google.com/books?id=UE6vFEnGP2kC |title=Digital Logic Techniques: Principles and Practice |date=1996 |page=174|publisher=Taylor & Francis |isbn=9780412549700 }}</ref> Following the development of [[silicon-gate]] MOS technology by [[Federico Faggin]] at Fairchild Semiconductor in 1968, MOS ICs largely replaced bipolar TTL as the standard chip technology in the late 1970s.<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=Computer History Museum |access-date=2019-08-16 |archive-date=2020-07-29 |archive-url=https://web.archive.org/web/20200729145834/https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |url-status=live }}</ref> | ||
As the [[microelectronic]] technology advanced, an increasing number of transistors were placed on ICs, decreasing the number of individual ICs needed for a complete CPU. MSI and LSI ICs increased transistor counts to hundreds, and then thousands. By 1968, the number of ICs required to build a complete CPU had been reduced to 24 ICs of eight different types, with each IC containing roughly 1000 MOSFETs.<ref>{{cite conference |first=R. K. |last=Booher |url=http://www.computer.org/csdl/proceedings/afips/1968/5072/00/50720877.pdf |title=MOS GP Computer |publisher=[[AFIPS]] |page=877 |date=1968 |conference=International Workshop on Managing Requirements Knowledge | As the [[microelectronic]] technology advanced, an increasing number of transistors were placed on ICs, decreasing the number of individual ICs needed for a complete CPU. MSI and LSI ICs increased transistor counts to hundreds, and then thousands. By 1968, the number of ICs required to build a complete CPU had been reduced to 24 ICs of eight different types, with each IC containing roughly 1000 MOSFETs.<ref>{{cite conference |first=R. K. |last=Booher |url=http://www.computer.org/csdl/proceedings/afips/1968/5072/00/50720877.pdf |title=MOS GP Computer |publisher=[[AFIPS]] |page=877 |date=1968 |conference=International Workshop on Managing Requirements Knowledge | ||
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}} | }} | ||
[[File:Laptop-intel-core2duo-t5500.jpg|thumb|Inside of a laptop, with the CPU removed from socket]] | [[File:Laptop-intel-core2duo-t5500.jpg|thumb|Inside of a laptop, with the CPU removed from socket]] | ||
Since microprocessors were first introduced they have almost completely overtaken all other central processing unit implementation methods. The first commercially available microprocessor, made in 1971, was the [[Intel 4004]]. Intel 4004 was one of the first consumer-facing | Since microprocessors were first introduced they have almost completely overtaken all other central processing unit implementation methods. The first commercially available microprocessor, made in 1971, was the [[Intel 4004]]. The Intel 4004 was one of the first consumer-facing CPUs integrating [[arithmetic logic unit]], [[control unit]], and [[processor register|register unit]] on a chip.<ref>{{Cite web |title=Chip Hall of Fame: Intel 4004 Microprocessor - IEEE Spectrum |url=https://spectrum.ieee.org/chip-hall-of-fame-intel-4004-microprocessor |access-date=2025-08-10 |website=spectrum.ieee.org |language=en}}</ref> The first widely used microprocessor, made in 1974, was the [[Intel 8080]]. Mainframe and minicomputer manufacturers of the time launched proprietary IC development programs to upgrade their older [[computer architecture]]s, and eventually produced [[instruction set architecture|instruction set]] compatible microprocessors that were backward-compatible with their older hardware and software. Combined with the advent and eventual success of the ubiquitous [[personal computer]], the term ''CPU'' is now applied almost exclusively{{Efn|Integrated circuits are now used to implement all CPUs, except for a few machines designed to withstand large electromagnetic pulses, say from a nuclear weapon.}} to microprocessors. Several CPUs (denoted ''cores'') can be combined in a single processing chip.<ref>{{cite web |url=https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |publisher=TechTarget |title=What is a multicore processor and how does it work? |first=Stephen J. |last=Bigelow |date=March 2022 |access-date=July 17, 2022 |archive-date=July 11, 2022 |archive-url=https://web.archive.org/web/20220711210214/https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |url-status=live }}</ref> | ||
{{anchor|DISCRETE-PROCESSOR}} | {{anchor|DISCRETE-PROCESSOR}} | ||
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===Control unit=== | ===Control unit=== | ||
{{main|Control unit}} | {{main|Control unit}} | ||
The | The control unit (CU) is a component of the CPU that directs the operation of the processor. It tells the computer's memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor. | ||
It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. [[John von Neumann]] included the control unit as part of the [[von Neumann architecture]]. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.<ref>{{Cite web|date=2018-09-24|title=Introduction of Control Unit and its Design|url=https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|access-date=2021-01-12|website=GeeksforGeeks|language=en-US|archive-date=2021-01-15|archive-url=https://web.archive.org/web/20210115072904/https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|url-status=live}}</ref> | It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. [[John von Neumann]] included the control unit as part of the [[von Neumann architecture]]. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.<ref>{{Cite web|date=2018-09-24|title=Introduction of Control Unit and its Design|url=https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|access-date=2021-01-12|website=GeeksforGeeks|language=en-US|archive-date=2021-01-15|archive-url=https://web.archive.org/web/20210115072904/https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|url-status=live}}</ref> | ||
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===Arithmetic logic unit=== | ===Arithmetic logic unit=== | ||
{{Main|Arithmetic logic unit}} | {{Main|Arithmetic logic unit}} | ||
[[File:ALU block. | [[File:ALU block.svg|thumb|upright=1.3|Symbolic representation of an ALU and its input and output signals]] | ||
The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and [[bitwise logic]] operations. The inputs to the ALU are the data words to be operated on (called [[operands]]), status information from previous operations, and a code from the control unit indicating which operation to perform. Depending on the instruction being executed, the operands may come from [[processor register|internal CPU registers]], external memory, or constants generated by the ALU itself. | The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and [[bitwise logic]] operations. The inputs to the ALU are the data words to be operated on (called [[operands]]), status information from previous operations, and a code from the control unit indicating which operation to perform. Depending on the instruction being executed, the operands may come from [[processor register|internal CPU registers]], external memory, or constants generated by the ALU itself. | ||
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While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of [[array element]]s must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different [[integer arithmetic operation]]s, such as addition, subtraction, [[modulo operation]]s, or [[bit shift]]s. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily [[Instruction cycle|decode and execute]] quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle. | While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of [[array element]]s must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different [[integer arithmetic operation]]s, such as addition, subtraction, [[modulo operation]]s, or [[bit shift]]s. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily [[Instruction cycle|decode and execute]] quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle. | ||
Capabilities of an AGU depend on a particular CPU and its [[Computer architecture|architecture]]. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple [[operand]]s at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the [[superscalar]] nature of advanced CPU designs. For example, [[Intel]] incorporates multiple AGUs into its [[ | Capabilities of an AGU depend on a particular CPU and its [[Computer architecture|architecture]]. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple [[operand]]s at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the [[superscalar]] nature of advanced CPU designs. For example, [[Intel]] incorporates multiple AGUs into its [[Sandy Bridge]] and [[Haswell (microarchitecture)|Haswell]] [[microarchitecture]]s, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel. | ||
===Memory management unit (MMU)=== | ===Memory management unit (MMU)=== | ||
{{Main|Memory management unit}} | {{Main|Memory management unit}} | ||
Many microprocessors (in smartphones and desktop, laptop, server computers) have a memory management unit, translating logical addresses into physical RAM addresses, providing [[memory protection]] and [[paging]] abilities, useful for [[virtual memory]]. Simpler processors, especially [[microcontroller]]s, usually | Many microprocessors (in smartphones and desktop, laptop, server computers) have a memory management unit (MMU), translating logical addresses into physical RAM addresses, providing [[memory protection]] and [[paging]] abilities, useful for [[virtual memory]]. The MMU is usually integrated in the processor but in some cases it is in a separate integrated circuit (IC).<ref>{{Cite web |date=2024-02-13 |title=What is Memory Management Unit(MMU)? |url=https://www.geeksforgeeks.org/computer-organization-architecture/what-is-memory-management-unit/ |access-date=2025-09-25 |website=GeeksforGeeks |language=en-US}}</ref> Simpler processors, especially [[microcontroller]]s, usually do not include an MMU. | ||
===Cache=== | ===Cache=== | ||
A [[CPU cache]]<ref>{{cite web |author=Torres |first=Gabriel |date=September 12, 2007 |title=How The Cache Memory Works |url=https://hardwaresecrets.com/how-the-cache-memory-works/ |access-date=January 29, 2023 |website=Hardware Secrets}}</ref> | A [[CPU cache]] is a memory used by the central processing unit (CPU) of a [[computer]] to reduce the average cost (time or energy) to access [[Data (computing)|data]] from the [[main memory]].<ref>{{cite web |author=Torres |first=Gabriel |date=September 12, 2007 |title=How The Cache Memory Works |url=https://hardwaresecrets.com/how-the-cache-memory-works/ |access-date=January 29, 2023 |website=Hardware Secrets}}</ref> A cache is a smaller, faster memory, closer to a [[processor core]], which stores copies of the data from frequently used main [[memory location]]s. Most CPUs have different independent caches, usually organized as a hierarchy of several cache levels (L1, L2, L3, L4, etc.). Each ascending cache level is typically slower but larger than the preceding level with L1 being the fastest and the closest to the CPU. At the L1 level there are usually separate [[Instruction cache|instruction]] and [[data cache]]s. | ||
Most modern (fast) CPUs (with few specialized exceptions{{efn|A few specialized CPUs, accelerators or microcontrollers do not have a cache. To be fast, if needed/wanted, they still have an on-chip scratchpad memory that has a similar function, while software managed. In e.g. microcontrollers it can be better for hard real-time use, to have that or at least no cache, as with one level of memory latencies of loads are predictable.}}) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a [[multi-core processor]] has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on [[dynamic random-access memory]] (DRAM), rather than on [[static random-access memory]] (SRAM), on a separate die or chip. That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and is optimized differently. | |||
Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the [[translation lookaside buffer]] (TLB) that is part of the [[memory management unit]] (MMU) that most CPUs have. | Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the [[translation lookaside buffer]] (TLB) that is part of the [[memory management unit]] (MMU) that most CPUs have. | ||
Caches are generally sized in powers of two: 2, 8, 16 etc. [[Kibibyte|KiB]] or [[Mebibyte|MiB]] (for larger non-L1) sizes, although the [[IBM z13 (microprocessor)|IBM z13]] has a 96 KiB L1 instruction cache.<ref>{{cite web|url=http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-date=2022-10-09 |url-status=live|title=IBM z13 and IBM z13s Technical Introduction|page=20|date=March 2016|publisher=[[IBM | Caches are generally sized in powers of two: 2, 8, 16 etc. [[Kibibyte|KiB]] or [[Mebibyte|MiB]] (for larger non-L1) sizes, although the [[IBM z13 (microprocessor)|IBM z13]] has a 96 KiB L1 instruction cache.<ref>{{cite web|url=http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-date=2022-10-09 |url-status=live|title=IBM z13 and IBM z13s Technical Introduction|page=20|date=March 2016|publisher=[[IBM]]}}</ref> | ||
===Clock rate=== | ===Clock rate=== | ||
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===Clockless CPUs=== | ===Clockless CPUs=== | ||
Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and [[heat dissipation]] in comparison with similar synchronous designs. While somewhat uncommon, entire [[Asynchronous circuit#Asynchronous CPU|asynchronous CPUs]] have been built without using a global clock signal. Two notable examples of this are the [[ARM architecture family|ARM]] compliant [[AMULET microprocessor|AMULET]] and the [[MIPS architecture|MIPS]] R3000 compatible MiniMIPS.<ref | Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and [[heat dissipation]] in comparison with similar synchronous designs. While somewhat uncommon, entire [[Asynchronous circuit#Asynchronous CPU|asynchronous CPUs]] have been built without using a global clock signal. Two notable examples of this are the [[ARM architecture family|ARM]] compliant [[AMULET microprocessor|AMULET]] and the [[MIPS architecture|MIPS]] R3000 compatible MiniMIPS.<ref>{{Cite journal |last1=Martin |first1=A. J. |last2=Nystrom |first2=M. |last3=Wong |first3=C. G. |date=November 2003 |title=Three generations of asynchronous microprocessors |journal=IEEE Design & Test of Computers |volume=20 |issue=6 |pages=9–17 |doi=10.1109/MDT.2003.1246159 |bibcode=2003IDTC...20....9M |issn=0740-7475 |s2cid=15164301 }}</ref> | ||
Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous [[Arithmetic logic unit|ALUs]] in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for [[embedded computer]]s.<ref>{{cite conference |author1=Garside, J. D. |author2=Furber, S. B. |author3= Chung, S-H | title = AMULET3 Revealed | publisher = [[University of Manchester]] Computer Science Department | year = 1999 | url = http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php |book-title=Proceedings, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems |doi=10.1109/ASYNC.1999.761522 | archive-url=https://web.archive.org/web/20051210205845/http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php | archive-date=December 10, 2005 | url-status=dead| url-access=subscription }}</ref> | Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous [[Arithmetic logic unit|ALUs]] in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for [[embedded computer]]s.<ref>{{cite conference |author1=Garside, J. D. |author2=Furber, S. B. |author3= Chung, S-H | title = AMULET3 Revealed | publisher = [[University of Manchester]] Computer Science Department | year = 1999 | url = http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php |book-title=Proceedings, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems |doi=10.1109/ASYNC.1999.761522 | archive-url=https://web.archive.org/web/20051210205845/http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php | archive-date=December 10, 2005 | url-status=dead| url-access=subscription }}</ref> | ||
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====Task-level parallelism==== | ====Task-level parallelism==== | ||
{{Main|Multithreading (computer architecture)|l1=Multithreading|Multi-core processor}} | {{Main|Multithreading (computer architecture)|l1=Multithreading|Multi-core processor}} | ||
Another strategy of achieving performance is to execute multiple [[Thread (computing)|threads]] or [[Process (computing)|processes]] in parallel. This area of research is known as [[parallel computing]].<ref>{{cite book |last1=Gottlieb |first1=Allan |url=http://dl.acm.org/citation.cfm?id=160438 |title=Highly parallel computing |last2=Almasi |first2=George S. |publisher=Benjamin/Cummings |year=1989 |isbn=978-0-8053-0177-9 |location=Redwood City, California |language=en-us |access-date=2016-04-25 |archive-url=https://web.archive.org/web/20181107043726/https://dl.acm.org/citation.cfm?id=160438 |archive-date=2018-11-07 |url-status=live}}</ref> In [[Flynn's taxonomy]], this strategy is known as [[Multiple instruction, multiple data|multiple instruction stream, multiple data stream]] (MIMD).<ref>{{Cite journal|last1=Flynn|first1=M. J. |s2cid=18573685 |author-link1=Michael J. Flynn|doi=10.1109/TC.1972.5009071|title=Some Computer Organizations and Their Effectiveness|journal=[[IEEE Transactions on Computers]]|volume=C-21|issue=9| pages=948–960| date=September 1972}}</ref> | Another strategy of achieving performance is to execute multiple [[Thread (computing)|threads]] or [[Process (computing)|processes]] in parallel. This area of research is known as [[parallel computing]].<ref>{{cite book |last1=Gottlieb |first1=Allan |url=http://dl.acm.org/citation.cfm?id=160438 |title=Highly parallel computing |last2=Almasi |first2=George S. |publisher=Benjamin/Cummings |year=1989 |isbn=978-0-8053-0177-9 |location=Redwood City, California |language=en-us |access-date=2016-04-25 |archive-url=https://web.archive.org/web/20181107043726/https://dl.acm.org/citation.cfm?id=160438 |archive-date=2018-11-07 |url-status=live}}</ref> In [[Flynn's taxonomy]], this strategy is known as [[Multiple instruction, multiple data|multiple instruction stream, multiple data stream]] (MIMD).<ref>{{Cite journal|last1=Flynn|first1=M. J. |s2cid=18573685 |author-link1=Michael J. Flynn|doi=10.1109/TC.1972.5009071|title=Some Computer Organizations and Their Effectiveness|journal=[[IEEE Transactions on Computers]]|volume=C-21|issue=9| pages=948–960| date=September 1972 |bibcode=1972ITCmp.100..948F }}</ref> | ||
One technology used for this purpose is [[multiprocessing]] (MP).<ref>{{cite journal |last1=Lu |first1=N.-P. |last2=Chung |first2=C.-P. |year=1998 |title=Parallelism exploitation in superscalar multiprocessing | One technology used for this purpose is [[multiprocessing]] (MP).<ref>{{cite journal |last1=Lu |first1=N.-P. |last2=Chung |first2=C.-P. |year=1998 |title=Parallelism exploitation in superscalar multiprocessing |url=https://digital-library.theiet.org/doi/10.1049/ip-cdt%3A19981955 |journal=IEE Proceedings - Computers and Digital Techniques |volume=145 |issue=4 |pages=255 |doi=10.1049/ip-cdt:19981955|doi-broken-date=11 July 2025 |url-access=subscription }}</ref> The initial type of this technology is known as [[symmetric multiprocessing]] (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate on the same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful, schemes such as [[non-uniform memory access]] (NUMA) and [[directory-based coherence protocols]] were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When the processors and their interconnect are all implemented on a single chip, the technology is known as chip-level multiprocessing (CMP) and the single chip as a [[multi-core processor]]. | ||
It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented [[input/output]] processing such as [[direct memory access]] as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as [[Multithreading (computer architecture)|multi-threading]] (MT). The approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU are replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as [[temporal multithreading]], where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the [[UltraSPARC T1]]. Another type of MT is [[simultaneous multithreading]], where instructions from multiple threads are executed in parallel within one CPU clock cycle. | It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented [[input/output]] processing such as [[direct memory access]] as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as [[Multithreading (computer architecture)|multi-threading]] (MT). The approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU are replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as [[temporal multithreading]], where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the [[UltraSPARC T1]]. Another type of MT is [[simultaneous multithreading]], where instructions from multiple threads are executed in parallel within one CPU clock cycle. | ||
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vCPU is not to be confused with a [[virtual private server]] (VPS). | vCPU is not to be confused with a [[virtual private server]] (VPS). | ||
A host is the virtual equivalent of a physical machine, on which a virtual system is operating.<ref>{{Cite web |date=2006 |title=VMware Infrastructure Architecture Overview – White Paper |url=https://www.vmware.com/pdf/vi_architecture_wp.pdf |url-status= | A host is the virtual equivalent of a physical machine, on which a virtual system is operating.<ref>{{Cite web |date=2006 |title=VMware Infrastructure Architecture Overview – White Paper |url=https://www.vmware.com/pdf/vi_architecture_wp.pdf |url-status=dead |archive-url=https://ghostarchive.org/archive/20221009/https://www.vmware.com/pdf/vi_architecture_wp.pdf |archive-date=2022-10-09 |website=VMware}}</ref> When there are several physical machines operating in tandem and managed as a whole, the grouped computing and memory resources form a [[Computer cluster|cluster]]. In some systems, it is possible to dynamically add and remove from a cluster. Resources available at a host and cluster level can be partitioned into [[Pool (computer science)|resources pools]] with fine [[Granularity (parallel computing)|granularity]]. | ||
=={{anchor|PCM}}Performance== | =={{anchor|PCM}}Performance== | ||
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}}</ref> | }}</ref> | ||
Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the [[memory hierarchy]] also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, various standardized tests, often called [[benchmark (computing)| | Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the [[memory hierarchy]] also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, various standardized tests, often called "[[benchmark (computing)|benchmarks]]" for this purpose{{snd}}such as [[SPECint]]{{snd}}have been developed to attempt to measure the real effective performance in commonly used applications. | ||
Processing performance of computers is increased by using [[multi-core processor]]s, which essentially is plugging two or more individual processors (called ''cores'' in this sense) into one integrated circuit.<ref name="tt">{{Cite web | Processing performance of computers is increased by using [[multi-core processor]]s, which essentially is plugging two or more individual processors (called ''cores'' in this sense) into one integrated circuit.<ref name="tt">{{Cite web | ||
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| archive-date = 5 August 2010 | | archive-date = 5 August 2010 | ||
| archive-url = https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html | | archive-url = https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html | ||
| url-status = | | url-status = dead | ||
}}</ref> Ideally, a dual core processor would be nearly twice as powerful as a single core processor. In practice, the performance gain is far smaller, only about 50%, due to imperfect software algorithms and implementation.<ref>{{cite news|url=https://techspirited.com/quad-core-vs-dual-core|title=Quad Core Vs. Dual Core|newspaper=Tech Spirited |date=8 April 2010|access-date=7 November 2019|archive-date=4 July 2019|archive-url=https://web.archive.org/web/20190704093754/https://techspirited.com/quad-core-vs-dual-core|url-status=live |author1=Mlblevins }}</ref> Increasing the number of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can be handled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought of as different floors in a processing plant, with each floor handling a different task. Sometimes, these cores will handle the same tasks as cores adjacent to them if a single core is not enough to handle the information. Multi-core CPUs enhance a computer's ability to run several tasks simultaneously by providing additional processing power. However, the increase in speed is not directly proportional to the number of cores added. This is because the cores need to interact through specific channels, and this inter-core communication consumes a portion of the available processing speed.<ref>{{Cite web |last=Marcin |first=Wieclaw |date=12 January 2022 |title=Factors Affecting Multi-Core Processors Performance |url=https://pcsite.co.uk/factors-affecting-multi-core-central-processing-unit-performance/ |website=PcSite}}</ref> | }}</ref> Ideally, a dual core processor would be nearly twice as powerful as a single core processor. In practice, the performance gain is far smaller, only about 50%, due to imperfect software algorithms and implementation.<ref>{{cite news|url=https://techspirited.com/quad-core-vs-dual-core|title=Quad Core Vs. Dual Core|newspaper=Tech Spirited |date=8 April 2010|access-date=7 November 2019|archive-date=4 July 2019|archive-url=https://web.archive.org/web/20190704093754/https://techspirited.com/quad-core-vs-dual-core|url-status=live |author1=Mlblevins }}</ref> Increasing the number of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can be handled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought of as different floors in a processing plant, with each floor handling a different task. Sometimes, these cores will handle the same tasks as cores adjacent to them if a single core is not enough to handle the information. Multi-core CPUs enhance a computer's ability to run several tasks simultaneously by providing additional processing power. However, the increase in speed is not directly proportional to the number of cores added. This is because the cores need to interact through specific channels, and this inter-core communication consumes a portion of the available processing speed.<ref>{{Cite web |last=Marcin |first=Wieclaw |date=12 January 2022 |title=Factors Affecting Multi-Core Processors Performance |url=https://pcsite.co.uk/factors-affecting-multi-core-central-processing-unit-performance/ |website=PcSite}}</ref> | ||
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==Overclocking== | ==Overclocking== | ||
[[File:RTX 4070 Ti SUPER im Vergleich mit anderen RTX 40er-Karten (极客湾Geekerwan) 005.png|thumb|Nvidia-Asus Tuf GPUs that | [[File:RTX 4070 Ti SUPER im Vergleich mit anderen RTX 40er-Karten (极客湾Geekerwan) 005.png|thumb|Nvidia-Asus Tuf GPUs that have OG (original) and OC (overclockable) on them]] | ||
{{Main|Overclocking}} | {{Main|Overclocking}} | ||
[[Overclocking]] is a process of increasing the [[clock rate|clock speed]] of a CPU (and other components) to | [[Overclocking]] is a process of increasing the [[clock rate|clock speed]] of a CPU (and other components) beyond their rated speeds. Increasing a component's clock rate causes it to perform more operations per second.<ref>{{Cite conference |last1=Thomas |first1=Diljo |last2=Shanmugasundaram |first2=M |title=A Survey on Different Overclocking Methods |date=March 2018 |conference=2018 Second International Conference on Electronics, Communication and Aerospace Technology (ICECA) |pages=1588–1592 |doi=10.1109/ICECA.2018.8474921 |isbn=978-1-5386-0965-1 }}</ref> Overclocking might increase CPU temperature and cause it to [[Overheating (electricity)|overheat]], so most users do not overclock and leave the clock speed unchanged. Some versions of components (such as [[Intel Core|Intel's U version of its CPUs]] or [[Nvidia RTX|Nvidia's OG]] GPUs) do not allow overclocking. | ||
==See also== | ==See also== | ||