Control unit: Difference between revisions

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~~The~~ '''control unit''' ('''CU''') is a component of a computer's [[central processing unit]] (CPU) that directs the operation of the processor. A CU typically uses a [[binary decoder]] to convert coded instructions into timing and control signals that direct the operation of the other units (memory, [[arithmetic logic unit]] and input and output devices, etc.).

In [[Computer architecture#Subcategories|computer architecture]], the '''control unit''' ('''CU''') is a component of a computer's [[central processing unit]] (CPU) that directs the operation of the processor. A CU typically uses a [[binary decoder]] to convert coded instructions into timing and control signals that direct the operation of the other units (memory, [[arithmetic logic unit]] and input and output devices, etc.).

Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. [[John von Neumann]] included the control unit as part of the [[von Neumann architecture]].<ref>{{Citation|last1=von Neumann |first1=John |title=First Draft of a Report on the EDVAC |year=1945 |publisher=Moore School of Electrical Engineering, University of Pennsylvania |url=http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf |url-status=dead |archive-url=https://web.archive.org/web/20130314123032/http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf |archive-date=March 14, 2013 }}</ref> In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.<ref>{{cite web|url=https://www.geeksforgeeks.org/computer-organization-control-unit-and-design/|title=Computer Organization - Control Unit and design|website=GeeksforGeeks|author=Astha Singh|date=24 September 2018 |access-date=25 May 2019}}</ref>

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In a pipelined computer, the control unit arranges for the flow to start, continue, and stop as a program commands. The instruction data is usually passed in pipeline registers from one stage to the next, with a somewhat separated piece of control logic for each stage. The control unit also assures that the instruction in each stage does not harm the operation of instructions in other stages. For example, if two stages must use the same piece of data, the control logic assures that the uses are done in the correct sequence.

When operating efficiently, a pipelined computer will have an instruction in each stage. It is then working on all of those instructions at the same time. It can finish about one instruction for each cycle of its clock. When a program makes a decision, and switches to a different sequence of instructions, the pipeline sometimes must discard the data in process and restart. This is called a "stall." When two instructions could interfere, sometimes the control unit must stop processing a later instruction until an earlier instruction completes. This is called a "pipeline bubble" because a part of the pipeline is not processing instructions. Pipeline bubbles can occur when two instructions operate on the same register.

When operating efficiently, a pipelined computer will have an instruction in each stage. It is then working on all of those instructions at the same time. It can finish about one instruction for each cycle of its clock. When a program makes a decision, and switches to a different sequence of instructions, the pipeline sometimes must discard the data in process and restart. This is called a "stall". When two instructions could interfere, sometimes the control unit must stop processing a later instruction until an earlier instruction completes. This is called a "pipeline bubble" because a part of the pipeline is not processing instructions. Pipeline bubbles can occur when two instructions operate on the same register.

Interrupts and unexpected exceptions also stall the pipeline. If a pipelined computer abandons work for an interrupt, more work is lost than in a multicycle computer. Predictable exceptions do not need to stall. For example, if an exception instruction is used to enter the operating system, it does not cause a stall.

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== Preventing stalls ==

Control units use many methods to keep a pipeline full and avoid stalls. For example, even simple control units can assume that a backwards branch, to a lower-numbered, earlier instruction, is a loop, and will be repeated.<ref name=riscv>{{cite book |last1=Asanovic |first1=Krste |author1-link=Krste Asanović |title=The RISC V Instruction Set Manual |date=2017 |publisher=RISC-V Foundation |location=Berkeley |edition=2.2 |url=https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf}}</ref> So, a control unit with this design will always fill the pipeline with the backwards branch path. If a [[compiler]] can detect the most frequently-taken direction of a branch, the compiler can just produce instructions so that the most frequently taken branch is the preferred direction of branch. In a like way, a control unit might get hints from the compiler: Some computers have instructions that can encode hints from the compiler about the direction of branch.<ref>{{cite book |title=Power ISA~~(tm)~~ |date=2017 |publisher=IBM |location=Austin |edition=3.0B |url=https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv |access-date=26 December 2019}}</ref>

Control units use many methods to keep a pipeline full and avoid stalls. For example, even simple control units can assume that a backwards branch, to a lower-numbered, earlier instruction, is a loop, and will be repeated.<ref name=riscv>{{cite book |last1=Asanovic |first1=Krste |author1-link=Krste Asanović |title=The RISC V Instruction Set Manual |date=2017 |publisher=RISC-V Foundation |location=Berkeley |edition=2.2 |url=https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf}}</ref> So, a control unit with this design will always fill the pipeline with the backwards branch path. If a [[compiler]] can detect the most frequently-taken direction of a branch, the compiler can just produce instructions so that the most frequently taken branch is the preferred direction of branch. In a like way, a control unit might get hints from the compiler: Some computers have instructions that can encode hints from the compiler about the direction of branch.<ref>{{cite book |title=Power ISA |date=2017 |publisher=IBM |location=Austin |edition=3.0B |url=https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv |access-date=26 December 2019}}</ref>

Some control units do [[Branch predictor|branch prediction]]: A control unit keeps an electronic list of the recent branches, encoded by the address of the branch instruction.<ref name=riscv /> This list has a few bits for each branch to remember the direction that was taken most recently.

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A control unit can be designed to [[Microarchitecture#Out-of-order execution|finish what it can]]. If several instructions can be completed at the same time, the control unit will arrange it. So, the fastest computers can process instructions in a sequence that can vary somewhat, depending on when the operands or instruction destinations become available. Most supercomputers and many PC CPUs use this method. The exact organization of this type of control unit depends on the slowest part of the computer.

When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called "issue units." An issue unit holds an instruction until both its operands and an execution unit are available. Then, the instruction and its operands are "issued" to an execution unit. The execution unit does the instruction. Then the resulting data is moved into a queue of data to be written back to memory or registers. If the computer has multiple execution units, it can usually do several instructions per clock cycle.

When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called "issue units". An issue unit holds an instruction until both its operands and an execution unit are available. Then, the instruction and its operands are "issued" to an execution unit. The execution unit does the instruction. Then the resulting data is moved into a queue of data to be written back to memory or registers. If the computer has multiple execution units, it can usually do several instructions per clock cycle.

It is common to have specialized execution units. For example, a modestly priced computer might have only one floating-point execution unit, because floating point units are expensive. The same computer might have several integer units, because these are relatively inexpensive, and can do the bulk of instructions.

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Managing leakage is more difficult, because before the logic can be turned-off, the data in it must be moved to some type of low-leakage storage.

Some CPUs<ref name="armv6">{{cite book |title=The ARM~~(tm)~~ Technical Reference Manual |publisher=ARM Ltd. |location=Cambridge |edition=v6, r0}}</ref> make use of a special type of flip-flop (to store a bit) that couples a fast, high-leakage storage cell to a slow, large (expensive) low-leakage cell. These two cells have separated power supplies. When the CPU enters a power saving mode (e.g. because of a halt that waits for an interrupt), data is transferred to the low-leakage cells, and the others are turned off. When the CPU leaves a low-leakage mode (e.g. because of an interrupt), the process is reversed.

Some CPUs<ref name="armv6">{{cite book |title=The ARM Technical Reference Manual |publisher=ARM Ltd. |location=Cambridge |edition=v6, r0}}</ref> make use of a special type of flip-flop (to store a bit) that couples a fast, high-leakage storage cell to a slow, large (expensive) low-leakage cell. These two cells have separated power supplies. When the CPU enters a power saving mode (e.g. because of a halt that waits for an interrupt), data is transferred to the low-leakage cells, and the others are turned off. When the CPU leaves a low-leakage mode (e.g. because of an interrupt), the process is reversed.

Older designs would copy the CPU state to memory, or even disk, sometimes with specialized software. Very simple embedded systems sometimes just restart.

== Integrating with the ~~Computer~~ ==

== Integrating with the computer ==

All modern CPUs have control logic to attach the CPU to the rest of the computer. In modern computers, this is usually a bus controller. When an instruction reads or writes memory, the control unit either controls the bus directly, or controls a bus controller. Many modern computers use the same bus interface for memory, input and output. This is called "memory-mapped I/O". To a programmer, the registers of the I/O devices appear as numbers at specific memory addresses. [[x86]] PCs use an older method, a separate I/O bus accessed by I/O instructions.

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A modern CPU also tends to include an [[interrupt]] controller. It handles interrupt signals from the system bus. The control unit is the part of the computer that responds to the interrupts.

There is often a cache controller to [[cache memory]]. The cache controller and the associated cache memory is often the largest physical part of a modern, higher-performance CPU. When the memory, bus or cache is shared with other CPUs, the control logic must communicate with them to assure that no computer ever gets out-of-date ~~old~~ data.

There is often a cache controller to [[cache memory]]. The cache controller and the associated cache memory is often the largest physical part of a modern, higher-performance CPU. When the memory, bus or cache is shared with other CPUs, the control logic must communicate with them to assure that no computer ever gets out-of-date data.

Many historic computers built some type of input and output directly into the control unit. For example, many historic computers had a front panel with switches and lights directly controlled by the control unit. These let a programmer directly enter a program and debug it. In later production computers, the most common use of a front panel was to enter a small bootstrap program to read the operating system from disk. ~~This was annoying. So, front~~ panels were replaced by [[BIOS|bootstrap program]]s in read-only memory.

Many historic computers built some type of input and output directly into the control unit. For example, many historic computers had a front panel with switches and lights directly controlled by the control unit. These let a programmer directly enter a program and debug it. In later production computers, the most common use of a front panel was to enter a small bootstrap program to read the operating system from disk. Front panels were replaced by [[BIOS|bootstrap program]]s in read-only memory.

Most [[PDP-8]] models had a data bus designed to let I/O devices borrow the control unit's memory read and write logic.<ref>{{cite book |title=PDP-8L Maintenance Manual |~~date~~=1970 |publisher=Digital Equipment Corp. |location=Maynard Mass. |url=http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-url=https://web.archive.org/web/20150422211242/http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-date=2015~~-04-22~~ |url-status=live |access-date=26 December 2019}}</ref> This reduced the complexity and expense of high speed I/O controllers, e.g. for disk.

Most [[PDP-8]] models had a data bus designed to let I/O devices borrow the control unit's memory read and write logic.<ref>{{cite book |title=PDP-8L Maintenance Manual |year=1970 |publisher=Digital Equipment Corp. |location=Maynard Mass. |url=http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-url=https://web.archive.org/web/20150422211242/http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-date=22 April 2015 |url-status=live |access-date=26 December 2019}}</ref> This reduced the complexity and expense of high speed I/O controllers, e.g. for disk.

The [[Xerox Alto]] had a multitasking microprogrammable control unit that performed almost all I/O.<ref>{{cite book |title=Alto Hardware Manual |~~date~~=1976 |publisher=Xerox |url=http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-url=https://web.archive.org/web/20101207201936/http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-date=2010~~-12-07~~ |url-status=live}}</ref> This design provided most of the features of a modern PC with only a tiny fraction of the electronic logic. The dual-thread computer was run by the two lowest-priority microthreads. These performed calculations whenever I/O was not required. High priority microthreads provided (in decreasing priority) video, network, disk, a periodic timer, mouse, and keyboard. The microprogram did the complex logic of the I/O device, as well as the logic to integrate the device with the computer. For the actual hardware I/O, the microprogram read and ~~wrote~~ shift registers for most I/O, sometimes with resistor networks and transistors to shift output voltage levels (e.g. for video). To handle outside events, the microcontroller had microinterrupts to switch threads at the end of a thread's cycle, e.g. at the end of an instruction, or after a shift-register was accessed. The microprogram could be rewritten and reinstalled, which was very useful for a research computer.

The [[Xerox Alto]] had a multitasking microprogrammable control unit that performed almost all I/O.<ref>{{cite book |title=Alto Hardware Manual |year=1976 |publisher=Xerox |url=http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-url=https://web.archive.org/web/20101207201936/http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-date=7 December 2010 |url-status=live}}</ref> This design provided most of the features of a modern PC with only a tiny fraction of the electronic logic. The dual-thread computer was run by the two lowest-priority microthreads. These performed calculations whenever I/O was not required. High priority microthreads provided (in decreasing priority) video, network, disk, a periodic timer, mouse, and keyboard. The microprogram did the complex logic of the I/O device, as well as the logic to integrate the device with the computer. For the actual hardware I/O, the microprogram read and write shift registers for most I/O, sometimes with resistor networks and transistors to shift output voltage levels (e.g. for video). To handle outside events, the microcontroller had microinterrupts to switch threads at the end of a thread's cycle, e.g. at the end of an instruction, or after a shift-register was accessed. The microprogram could be rewritten and reinstalled, which was very useful for a research computer.

== Functions of the control unit ==

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== External links ==

* Alexander Barkalov , Larysa Titarenko ,[https://link.springer.com/chapter/10.1007/978-3-642-04309-3_1 Hardwired Interpretation of Control Algorithms]

* [https://web.archive.org/web/20251010144449/https://www.ccbp.in/blog/articles/microprogrammed-control-unit-in-computer-organization Microprogrammed control Units]

* [https://www.cs.umd.edu/~meesh/cmsc311/clin-cmsc311/Lectures/lecture34/multi_control.pdf Multi-Cycle Control Units]

@@ Line 1: / Line 1: @@
 {{Short description|Component of a computer's CPU}}
-{{About|the component of a computer's CPU}}
+{{About|concept in computer hardware design}}
-The '''control unit''' ('''CU''') is a component of a computer's [[central processing unit]] (CPU) that directs the operation of the processor. A CU typically uses a [[binary decoder]] to convert coded instructions into timing and control signals that direct the operation of the other units (memory, [[arithmetic logic unit]] and input and output devices, etc.).
+In [[Computer architecture#Subcategories|computer architecture]], the '''control unit''' ('''CU''') is a component of a computer's [[central processing unit]] (CPU) that directs the operation of the processor. A CU typically uses a [[binary decoder]] to convert coded instructions into timing and control signals that direct the operation of the other units (memory, [[arithmetic logic unit]] and input and output devices, etc.).
 Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. [[John von Neumann]] included the control unit as part of the [[von Neumann architecture]].<ref>{{Citation|last1=von Neumann |first1=John |title=First Draft of a Report on the EDVAC |year=1945 |publisher=Moore School of Electrical Engineering, University of Pennsylvania |url=http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf |url-status=dead |archive-url=https://web.archive.org/web/20130314123032/http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf |archive-date=March 14, 2013 }}</ref> In modern computer designs, the control unit is typically an internal part of the CPU<!-- or other device that directs its operation--> with its overall role and operation unchanged since its introduction.<ref>{{cite web|url=https://www.geeksforgeeks.org/computer-organization-control-unit-and-design/|title=Computer Organization - Control Unit and design|website=GeeksforGeeks|author=Astha Singh|date=24 September 2018 |access-date=25 May 2019}}</ref>
@@ Line 34: / Line 34: @@
 In a pipelined computer, the control unit arranges for the flow to start, continue, and stop as a program commands. The instruction data is usually passed in pipeline registers from one stage to the next, with a somewhat separated piece of control logic for each stage. The control unit also assures that the instruction in each stage does not harm the operation of instructions in other stages.  For example, if two stages must use the same piece of data, the control logic assures that the uses are done in the correct sequence.
-When operating efficiently, a pipelined computer will have an instruction in each stage. It is then working on all of those instructions at the same time. It can finish about one instruction for each cycle of its clock. When a program makes a decision, and switches to a different sequence of instructions, the pipeline sometimes must discard the data in process and restart. This is called a "stall." When two instructions could interfere, sometimes the control unit must stop processing a later instruction until an earlier instruction completes. This is called a "pipeline bubble" because a part of the pipeline is not processing instructions. Pipeline bubbles can occur when two instructions operate on the same register.
+When operating efficiently, a pipelined computer will have an instruction in each stage. It is then working on all of those instructions at the same time. It can finish about one instruction for each cycle of its clock. When a program makes a decision, and switches to a different sequence of instructions, the pipeline sometimes must discard the data in process and restart. This is called a "stall". When two instructions could interfere, sometimes the control unit must stop processing a later instruction until an earlier instruction completes. This is called a "pipeline bubble" because a part of the pipeline is not processing instructions. Pipeline bubbles can occur when two instructions operate on the same register.
 Interrupts and unexpected exceptions also stall the pipeline. If a pipelined computer abandons work for an interrupt, more work is lost than in a multicycle computer.  Predictable exceptions do not need to stall. For example, if an exception instruction is used to enter the operating system, it does not cause a stall.
@@ Line 46: / Line 46: @@
 == Preventing stalls ==
-Control units use many methods to keep a pipeline full and avoid stalls. For example, even simple control units can assume that a backwards branch, to a lower-numbered, earlier instruction, is a loop, and will be repeated.<ref name=riscv>{{cite book |last1=Asanovic |first1=Krste |author1-link=Krste Asanović |title=The RISC V Instruction Set Manual |date=2017 |publisher=RISC-V Foundation |location=Berkeley |edition=2.2 |url=https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf}}</ref> So, a control unit with this design will always fill the pipeline with the backwards branch path. If a [[compiler]] can detect the most frequently-taken direction of a branch, the compiler can just produce instructions so that the most frequently taken branch is the preferred direction of branch. In a like way, a control unit might get hints from the compiler: Some computers have instructions that can encode hints from the compiler about the direction of branch.<ref>{{cite book |title=Power ISA(tm) |date=2017 |publisher=IBM |location=Austin |edition=3.0B |url=https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv |access-date=26 December 2019}}</ref>
+Control units use many methods to keep a pipeline full and avoid stalls. For example, even simple control units can assume that a backwards branch, to a lower-numbered, earlier instruction, is a loop, and will be repeated.<ref name=riscv>{{cite book |last1=Asanovic |first1=Krste |author1-link=Krste Asanović |title=The RISC V Instruction Set Manual |date=2017 |publisher=RISC-V Foundation |location=Berkeley |edition=2.2 |url=https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf}}</ref> So, a control unit with this design will always fill the pipeline with the backwards branch path. If a [[compiler]] can detect the most frequently-taken direction of a branch, the compiler can just produce instructions so that the most frequently taken branch is the preferred direction of branch. In a like way, a control unit might get hints from the compiler: Some computers have instructions that can encode hints from the compiler about the direction of branch.<ref>{{cite book |title=Power ISA |date=2017 |publisher=IBM |location=Austin |edition=3.0B |url=https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv |access-date=26 December 2019}}</ref>
 Some control units do [[Branch predictor|branch prediction]]: A control unit keeps an electronic list of the recent branches, encoded by the address of the branch instruction.<ref name=riscv /> This list has a few bits for each branch to remember the direction that was taken most recently.
@@ Line 64: / Line 64: @@
 A control unit can be designed to [[Microarchitecture#Out-of-order execution|finish what it can]]. If several instructions can be completed at the same time, the control unit will arrange it. So, the fastest computers can process instructions in a sequence that can vary somewhat, depending on when the operands or instruction destinations become available. Most supercomputers and many PC CPUs use this method. The exact organization of this type of control unit depends on the slowest part of the computer.
-When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called "issue units." An issue unit holds an instruction until both its operands and an execution unit are available. Then, the instruction and its operands are "issued" to an execution unit. The execution unit does the instruction. Then the resulting data is moved into a queue of data to be written back to memory or registers. If the computer has multiple execution units, it can usually do several instructions per clock cycle.
+When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called "issue units". An issue unit holds an instruction until both its operands and an execution unit are available. Then, the instruction and its operands are "issued" to an execution unit. The execution unit does the instruction. Then the resulting data is moved into a queue of data to be written back to memory or registers. If the computer has multiple execution units, it can usually do several instructions per clock cycle.
 It is common to have specialized execution units. For example, a modestly priced computer might have only one floating-point execution unit, because floating point units are expensive. The same computer might have several integer units, because these are relatively inexpensive, and can do the bulk of instructions.
@@ Line 106: / Line 106: @@
 Managing leakage is more difficult, because before the logic can be turned-off, the data in it must be moved to some type of low-leakage storage.
-Some CPUs<ref name="armv6">{{cite book |title=The ARM(tm) Technical Reference Manual |publisher=ARM Ltd. |location=Cambridge |edition=v6, r0}}</ref> make use of a special type of flip-flop (to store a bit) that couples a fast, high-leakage storage cell to a slow, large (expensive) low-leakage cell. These two cells have separated power supplies. When the CPU enters a power saving mode (e.g. because of a halt that waits for an interrupt), data is transferred to the low-leakage cells, and the others are turned off.  When the CPU leaves a low-leakage mode (e.g. because of an interrupt), the process is reversed.
+Some CPUs<ref name="armv6">{{cite book |title=The ARM Technical Reference Manual |publisher=ARM Ltd. |location=Cambridge |edition=v6, r0}}</ref> make use of a special type of flip-flop (to store a bit) that couples a fast, high-leakage storage cell to a slow, large (expensive) low-leakage cell. These two cells have separated power supplies. When the CPU enters a power saving mode (e.g. because of a halt that waits for an interrupt), data is transferred to the low-leakage cells, and the others are turned off.  When the CPU leaves a low-leakage mode (e.g. because of an interrupt), the process is reversed.
 Older designs would copy the CPU state to memory, or even disk, sometimes with specialized software. Very simple embedded systems sometimes just restart.
-== Integrating with the Computer ==
+== Integrating with the computer ==
 All modern CPUs have control logic to attach the CPU to the rest of the computer. In modern computers, this is usually a bus controller. When an instruction reads or writes memory, the control unit either controls the bus directly, or controls a bus controller. Many modern computers use the same bus interface for memory, input and output. This is called "memory-mapped I/O". To a programmer, the registers of the I/O devices appear as numbers at specific memory addresses. [[x86]] PCs use an older method, a separate I/O bus accessed by I/O instructions.
@@ Line 116: / Line 116: @@
 A modern CPU also tends to include an [[interrupt]] controller. It handles interrupt signals from the system bus. The control unit is the part of the computer that responds to the interrupts.
-There is often a cache controller to [[cache memory]]. The cache controller and the associated cache memory is often the largest physical part of a modern, higher-performance CPU. When the memory, bus or cache is shared with other CPUs, the control logic must communicate with them to assure that no computer ever gets out-of-date old data.
+There is often a cache controller to [[cache memory]]. The cache controller and the associated cache memory is often the largest physical part of a modern, higher-performance CPU. When the memory, bus or cache is shared with other CPUs, the control logic must communicate with them to assure that no computer ever gets out-of-date data.
-Many historic computers built some type of input and output directly into the control unit. For example, many historic computers had a front panel with switches and lights directly controlled by the control unit. These let a programmer directly enter a program and debug it. In later production computers, the most common use of a front panel was to enter a small bootstrap program to read the operating system from disk. This was annoying. So, front panels were replaced by [[BIOS|bootstrap program]]s in read-only memory.
+Many historic computers built some type of input and output directly into the control unit. For example, many historic computers had a front panel with switches and lights directly controlled by the control unit. These let a programmer directly enter a program and debug it. In later production computers, the most common use of a front panel was to enter a small bootstrap program to read the operating system from disk. Front panels were replaced by [[BIOS|bootstrap program]]s in read-only memory.
-Most [[PDP-8]] models had a data bus designed to let I/O devices borrow the control unit's memory read and write logic.<ref>{{cite book |title=PDP-8L Maintenance Manual |date=1970 |publisher=Digital Equipment Corp. |location=Maynard Mass. |url=http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-url=https://web.archive.org/web/20150422211242/http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-date=2015-04-22 |url-status=live |access-date=26 December 2019}}</ref> This reduced the complexity and expense of high speed I/O controllers, e.g. for disk.
+Most [[PDP-8]] models had a data bus designed to let I/O devices borrow the control unit's memory read and write logic.<ref>{{cite book |title=PDP-8L Maintenance Manual |year=1970 |publisher=Digital Equipment Corp. |location=Maynard Mass. |url=http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-url=https://web.archive.org/web/20150422211242/http://bitsavers.trailing-edge.com/pdf/dec/pdp8/pdp8l/DEC-8L-HR1B-D_8LmaintVol1.pdf |archive-date=22 April 2015 |url-status=live |access-date=26 December 2019}}</ref> This reduced the complexity and expense of high speed I/O controllers, e.g. for disk.
-The [[Xerox Alto]] had a multitasking microprogrammable control unit that performed almost all I/O.<ref>{{cite book |title=Alto Hardware Manual |date=1976 |publisher=Xerox |url=http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-url=https://web.archive.org/web/20101207201936/http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-date=2010-12-07 |url-status=live}}</ref> This design provided most of the features of a modern PC with only a tiny fraction of the electronic logic. The dual-thread computer was run by the two lowest-priority microthreads. These performed calculations whenever I/O was not required. High priority microthreads provided (in decreasing priority) video, network, disk, a periodic timer, mouse, and keyboard. The microprogram did the complex logic of the I/O device, as well as the logic to integrate the device with the computer. For the actual hardware I/O, the microprogram read and wrote shift registers for most I/O, sometimes with resistor networks and transistors to shift output voltage levels (e.g. for video). To handle outside events, the microcontroller had microinterrupts to switch threads at the end of a thread's cycle, e.g. at the end of an instruction, or after a shift-register was accessed. The microprogram could be rewritten and reinstalled, which was very useful for a research computer.
+The [[Xerox Alto]] had a multitasking microprogrammable control unit that performed almost all I/O.<ref>{{cite book |title=Alto Hardware Manual |year=1976 |publisher=Xerox |url=http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-url=https://web.archive.org/web/20101207201936/http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/Alto_Hardware_Manual_Aug76.pdf |archive-date=7 December 2010 |url-status=live}}</ref> This design provided most of the features of a modern PC with only a tiny fraction of the electronic logic. The dual-thread computer was run by the two lowest-priority microthreads. These performed calculations whenever I/O was not required. High priority microthreads provided (in decreasing priority) video, network, disk, a periodic timer, mouse, and keyboard. The microprogram did the complex logic of the I/O device, as well as the logic to integrate the device with the computer. For the actual hardware I/O, the microprogram read and write shift registers for most I/O, sometimes with resistor networks and transistors to shift output voltage levels (e.g. for video). To handle outside events, the microcontroller had microinterrupts to switch threads at the end of a thread's cycle, e.g. at the end of an instruction, or after a shift-register was accessed. The microprogram could be rewritten and reinstalled, which was very useful for a research computer.
 == Functions of the control unit ==
@@ Line 156: / Line 156: @@
 {{reflist}}
+== External links ==
+* Alexander Barkalov , Larysa Titarenko ,[https://link.springer.com/chapter/10.1007/978-3-642-04309-3_1 Hardwired Interpretation of Control Algorithms]
+* [https://web.archive.org/web/20251010144449/https://www.ccbp.in/blog/articles/microprogrammed-control-unit-in-computer-organization Microprogrammed control Units]
+* [https://www.cs.umd.edu/~meesh/cmsc311/clin-cmsc311/Lectures/lecture34/multi_control.pdf Multi-Cycle Control Units]
 {{CPU technologies}}

Control unit: Difference between revisions

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