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imported>RastaKins →The first x86 design: While the 8086 shares a similar architecture, 8086 does not have a MICROarchitecture similar to 08/80/85. 8086 has prefetching bus interface unit, execution unit, none of which those processors had. |
imported>RastaKins →Segmentation: Added a see also to x86 memory models |
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{{Short description|16-bit microprocessor}} | {{Short description|16-bit microprocessor}} | ||
{{Infobox CPU | {{Infobox CPU | ||
| name = Intel 8086 | | name = Intel 8086 | ||
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| caption = A rare Intel C8086 processor in purple ceramic DIP package with side-brazed pins | | caption = A rare Intel C8086 processor in purple ceramic DIP package with side-brazed pins | ||
| produced-start = 1978 | | produced-start = 1978 | ||
| produced-end = 1998<ref>{{Cite web |title=The Life Cycle of a CPU |url=https://www.cpushack.com/life-cycle-of-cpu.html |website=www.cpushack.com|access-date=26 January 2025}}</ref> | | produced-end = 1998<ref>{{Cite web |title=The Life Cycle of a CPU |url=https://www.cpushack.com/life-cycle-of-cpu.html |website=www.cpushack.com |access-date=26 January 2025 |archive-date=20 July 2021 |archive-url=https://web.archive.org/web/20210720004826/https://www.cpushack.com/life-cycle-of-cpu.html |url-status=live }}</ref> | ||
| slowest = 5 | slow-unit = MHz | | slowest = 5 | slow-unit = MHz | ||
| fastest = 10 | fast-unit = MHz | | fastest = 10 | fast-unit = MHz | ||
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| address-width = 20 bits | | address-width = 20 bits | ||
| sock1 = [[Dual in-line package|DIP40]] | | sock1 = [[Dual in-line package|DIP40]] | ||
| transistors=29, | | transistors=29,277<ref>{{cite web |title=Counting the transistors in the 8086 processor: it's harder than you might think |url=https://www.righto.com/2023/01/counting-transistors-in-8086-processor.html |publisher=Ken Sherriff |access-date=2026-01-27 |archive-date=2025-12-28 |archive-url=https://web.archive.org/web/20251228060243/https://www.righto.com/2023/01/counting-transistors-in-8086-processor.html |url-status=live }}</ref> | ||
| support status = Unsupported | | support status = Unsupported | ||
}} | }} | ||
The '''8086'''<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |access-date=2007-08-11 |archive-url=https://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/ |archive-date=2007-07-06}}</ref> (also called '''iAPX 86''')<ref name="i286">{{cite book|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference |page= 1-1 |publisher=Intel |year=1983}}</ref> is a [[16-bit computing|16-bit]] [[microprocessor]] chip | The '''8086'''<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |access-date=2007-08-11 |archive-url=https://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/ |archive-date=2007-07-06}}</ref> (also called '''iAPX 86''')<ref name="i286">{{cite book|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|page=1-1|publisher=Intel|year=1983|archive-date=2017-08-28|access-date=2017-08-28|archive-url=https://web.archive.org/web/20170828232803/http://www.bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|url-status=live}}</ref> is a [[16-bit computing|16-bit]] [[microprocessor]] chip released by [[Intel]] on June 8, 1978<ref name="Intel">{{cite press release|date=5 June 2018|url-status=dead|archive-url=https://web.archive.org/web/20230212150554/https://newsroom.intel.com/news/intel-i7-8086k-processor/|archive-date=12 February 2023|title=Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience|work=Intel Newsroom |url=https://newsroom.intel.com/news/intel-i7-8086k-processor/|publisher=Intel}}</ref> after development began in early 1976.<ref>{{Cite book |last=Šojat |first=Z. |last2=Skala |first2=K. |last3=Rogina |first3=B.M. |last4=Škoda |first4=P. |last5=Sović |first5=I. |editor-last1=Szewczyk |editor-first1=R. |chapter=Implementation of Advanced Historical Computer Architectures §2.5 Microprocessors |chapter-url=https://books.google.com/books?id=yM1sCwAAQBAJ&pg=PA67 |title=Embedded Engineering Education |editor-last2=Kaštelan |editor-first2=I. |editor-last3=Temerinac |editor-first3=M. |editor-last4=Barak |editor-first4=M. |editor-last5=Sruk |editor-first5=V. |date=2016 |publisher=Springer |isbn=978-3-319-27540-6 |language=en |archive-date=2025-11-13 |access-date=2025-08-04 |archive-url=https://web.archive.org/web/20251113021802/https://books.google.com/books?id=yM1sCwAAQBAJ&pg=PA67 |url-status=live }}</ref> It was followed by the [[Intel 8088]] in 1979,<ref>{{cite web|url=https://timeline.intel.com/1979/the-8088-processor|title=The 8088 Processor|website=timeline.intel.com|publisher=Intel|access-date=26 January 2025|archive-date=27 January 2025|archive-url=https://web.archive.org/web/20250127044825/https://timeline.intel.com/1979/the-8088-processor|url-status=live}}</ref> which was a slightly modified chip with an external 8-bit [[Bus (computing)|data bus]] (allowing the use of cheaper and fewer supporting [[Integrated circuit|IC]]s).<ref group="note">Fewer TTL buffers, latches, multiplexers (although the amount of TTL <u>logic</u> was not drastically reduced). It also permits the use of cheap 8080-family ICs, where the 8254 CTC, [[Intel 8255|8255]] PIO, and 8259 PIC were used in the IBM PC design. In addition, it makes PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref> | ||
The 8086 gave rise to the [[x86]] architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released a limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the [[Coffee Lake|Intel Core i7-8086K]].<ref name="Intel"/> | The 8086 gave rise to the [[x86]] architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released a limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the [[Coffee Lake#i7-8086K|Intel Core i7-8086K]].<ref name="Intel"/> | ||
==History== | ==History== | ||
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|title=8080 family | |title=8080 family | ||
|url=https://www.cpu-world.com/CPUs/8080/ | |url=https://www.cpu-world.com/CPUs/8080/ | ||
}}</ref> and also included some [[16-bit computing|16-bit]] instructions to make programming easier. The 8080 device was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]]-based [[Intel 8085|8085]] (1977), which used a single +5 V power supply instead of the three different operating voltages of earlier chips.<ref group="note">Made possible with depletion-load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086).</ref> Other well known 8-bit microprocessors that emerged during these years are [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978). | |access-date=2022-10-27 | ||
|archive-date=2022-10-27 | |||
|archive-url=https://web.archive.org/web/20221027234659/https://www.cpu-world.com/CPUs/8080/ | |||
|url-status=live | |||
}}</ref> and also included some [[16-bit computing|16-bit]] instructions to make programming easier. The 8080 device was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]]-based [[Intel 8085|8085]] (1977), which used a single +5 V power supply instead of the three different operating voltages of earlier chips.<ref group="note">Made possible with depletion-load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086).</ref> Other well known 8-bit microprocessors that emerged during these years are [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978). | |||
===The first x86 design=== | ===The first x86 design=== | ||
[[File:Intel 8086 CPU Die.JPG|thumb|Intel 8086 CPU die image]] | [[File:Intel 8086 CPU Die.JPG|thumb|Intel 8086 CPU die image]] | ||
The 8086 project started in May 1976<ref>{{Cite web |title=Birth of a standard: The Intel 8086 microprocessor turns 40 today |url=https://www.pcworld.com/article/535966/article-7512.html |access-date=2025-03-08 |website=PCWorld |language=en}}</ref> and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16-bit and [[32-bit computing|32-bit]] processors of other manufacturers — [[Motorola]], [[Zilog]], and [[National Semiconductor]]. | The 8086 project started in May 1976<ref>{{Cite web |title=Birth of a standard: The Intel 8086 microprocessor turns 40 today |url=https://www.pcworld.com/article/535966/article-7512.html |access-date=2025-03-08 |website=PCWorld |language=en |archive-date=2025-02-10 |archive-url=https://web.archive.org/web/20250210153844/https://www.pcworld.com/article/535966/article-7512.html |url-status=live }}</ref> and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16-bit and [[32-bit computing|32-bit]] processors of other manufacturers — [[Motorola]], [[Zilog]], and [[National Semiconductor]]. | ||
While the 8086 was a 16-bit microprocessor, it used a similar architecture as Intel's 8-bit microprocessors (8008, 8080, and 8085). This allowed [[assembly language]] programs written in 8-bit to [[Assembly language translator|seamlessly migrate]].<ref name="Scanlon_1988"/> New instructions and features — such as signed integers, base+offset addressing, and self-repeating operations — were added. Instructions were added to assist source code compilation of [[nested function]]s in the [[ALGOL]]-family of languages, including [[Pascal (programming language)|Pascal]] and [[PL/M]]. According to principal architect [[Stephen P. Morse]], this was a result of a more software-centric approach. Other enhancements included [[microcode]] instructions for the multiply and divide assembly language instructions. Designers also anticipated [[coprocessors]], such as [[Intel 8087|8087]] and [[Intel 8089|8089]], so the bus structure was designed to be flexible. | |||
The first revision of the instruction set and high level architecture was ready after about three months,<ref group="note" >Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip.<ref group="note" >Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered fast for a complex design in the 1970s. | The first revision of the instruction set and high level architecture was ready after about three months,<ref group="note" >Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip.<ref group="note" >Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered fast for a complex design in the 1970s. | ||
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The 8086 was die-shrunk to 2 μm in 1981; this version also corrected a stack register bug in the original 3.5 μm chips.{{clarification needed|date=April 2025}} Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house.{{citation needed|date=April 2025}} | The 8086 was die-shrunk to 2 μm in 1981; this version also corrected a stack register bug in the original 3.5 μm chips.{{clarification needed|date=April 2025}} Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house.{{citation needed|date=April 2025}} | ||
The architecture was defined by [[Stephen P. Morse]] with some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref group="note" >Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. | The architecture was defined by [[Stephen P. Morse]] with some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref group="note" >Other members of the design team were Peter A. Stoll and Jenny Hernandez.</ref> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. In addition, the [[PCI Configuration Space|PCI Vendor ID]] for system devices produced by Intel is 8086.<ref>{{Cite web |last= |first= |date=2025-08-04 |title=PCI\VEN_8086 - Intel Corporation |url=https://devicehunt.com/view/type/pci/vendor/8086 |access-date=2025-08-14 |website=Device Hunt |language=en |archive-date=2025-08-23 |archive-url=https://web.archive.org/web/20250823024439/https://devicehunt.com/view/type/pci/vendor/8086 |url-status=live }}</ref> | ||
==Details== | ==Details== | ||
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===Registers and instruction=== | ===Registers and instruction=== | ||
{| class="infobox" style="font-size:88%;width: | {| class="infobox" style="font-size:88%;width:35em;" | ||
|- | |- | ||
|+ Intel 8086 registers | |+ Intel 8086 registers | ||
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| style="text-align:center;" colspan="8"| AH | | style="text-align:center;" colspan="8"| AH | ||
| style="text-align:center;" colspan="8"| AL | | style="text-align:center;" colspan="8"| AL | ||
| style="background:white; color:black;"| '''[[Accumulator (computing)| | | style="background:white; color:black;"| '''AX''' [[Accumulator (computing)|(accumulator)]] | ||
|- style="background:silver;color:black" | |- style="background:silver;color:black" | ||
| style="text-align:center;background:white" colspan="4"| | |||
| style="text-align:center; background:white" colspan="4"| | |||
| style="text-align:center;" colspan="8"| CH | | style="text-align:center;" colspan="8"| CH | ||
| style="text-align:center;" colspan="8"| CL | | style="text-align:center;" colspan="8"| CL | ||
| style="background:white; color:black;"| '''CX''' (counter | | style="background:white; color:black;"| '''CX''' (counter) | ||
|- style="background:silver;color:black" | |- style="background:silver;color:black" | ||
| style="text-align:center; background:white" colspan="4"| | | style="text-align:center; background:white" colspan="4"| | ||
| style="text-align:center;" colspan="8"| DH | | style="text-align:center;" colspan="8"| DH | ||
| style="text-align:center;" colspan="8"| DL | | style="text-align:center;" colspan="8"| DL | ||
| style="background:white; color:black;"| '''DX''' ( | | style="background:white; color:black;"| '''DX''' (extended acc) | ||
|- style="background:silver;color:black" | |||
| style="text-align:center; background:#DDD" colspan="4"| 0 0 0 0 | |||
| style="text-align:center;" colspan="8"| BH | |||
| style="text-align:center;" colspan="8"| BL | |||
| style="background:white; color:black;"| '''BX''' (base) | |||
|- | |- | ||
|colspan="21" | '''Index registers''' <br /> | |colspan="21" | '''Index registers''' <br /> | ||
|- style="background:silver;color:black" | |||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | |||
| style="text-align:center;" colspan="16"| [[Stack register|SP]] | |||
| style="background:white; color:black;"| '''S'''tack '''P'''ointer | |||
|- style="background:silver;color:black" | |||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | |||
| style="text-align:center;" colspan="16"| BP | |||
| style="background:white; color:black;"| '''B'''ase '''P'''ointer | |||
|- style="background:silver;color:black" | |- style="background:silver;color:black" | ||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | | style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | ||
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| style="text-align:center;" colspan="16"| DI | | style="text-align:center;" colspan="16"| DI | ||
| style="background:white; color:black;"| '''D'''estination '''I'''ndex | | style="background:white; color:black;"| '''D'''estination '''I'''ndex | ||
|- | |- | ||
|colspan="21" | '''Program counter''' <br /> | |colspan="21" | '''Program counter''' <br /> | ||
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|- | |- | ||
|colspan="21" | '''Segment registers''' <br /> | |colspan="21" | '''Segment registers''' <br /> | ||
|- style="background:silver;color:black" | |||
| style="text-align:center;" colspan="16"| ES | |||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | |||
| style="background:white; color:black;"| '''E'''xtra '''S'''egment | |||
|- style="background:silver;color:black" | |- style="background:silver;color:black" | ||
| style="text-align:center;" colspan="16"| CS | | style="text-align:center;" colspan="16"| CS | ||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | | style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | ||
| style="background:white; color:black;"| '''C'''ode '''S'''egment | | style="background:white; color:black;"| '''C'''ode '''S'''egment | ||
|- style="background:silver;color:black" | |||
| style="text-align:center;" colspan="16"| SS | |||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | |||
| style="background:white; color:black;"| '''S'''tack '''S'''egment | |||
|- style="background:silver;color:black" | |- style="background:silver;color:black" | ||
| style="text-align:center;" colspan="16"| DS | | style="text-align:center;" colspan="16"| DS | ||
| style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | | style="text-align:center;background:#DDD" colspan="4"| 0 0 0 0 | ||
| style="background:white; color:black;"| '''D'''ata '''S'''egment | | style="background:white; color:black;"| '''D'''ata '''S'''egment | ||
|- | |- | ||
|colspan="21" | '''Status register''' | |colspan="21" | '''Status register''' | ||
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|} | |} | ||
|} | |} | ||
The 8086 has eight more-or-less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only. | The 8086 has eight more-or-less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.<ref name="Morse1982">{{cite book |last1=Morse |first1=Stephen P. |title=The 8086/8088 Primer: An Introduction to Their Architecture, System Design, and Programming |date=1982 |publisher=Hayden Book Co |location=Rochelle Park, N. J |isbn=0-8104-6255-9 |edition=2. |url=https://stevemorse.org/8086/8086.pdf |access-date=23 November 2025 |archive-date=10 February 2025 |archive-url=https://web.archive.org/web/20250210162345/https://stevemorse.org/8086/8086.pdf |url-status=live }}</ref> | ||
Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time. | Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time. | ||
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===Segmentation=== | ===Segmentation=== | ||
{{See also|x86 memory segmentation}} | {{See also|x86 memory segmentation}} | ||
There are also four 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, any external address could be referred to by up to 2<sup>12</sup> = 4096 different segment:offset pairs.<ref>{{cite web |last1=Sedory |first1=Daniel B|title=The Segment:Offset Addressing Scheme |url=https://thestarman.pcministry.com/asm/debug/Segments.html |website=thestarman.pcministry.com |access-date=6 March 2025}}</ref> | There are also four 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, any external address could be referred to by up to 2<sup>12</sup> = 4096 different segment:offset pairs.<ref>{{cite web |last1=Sedory |first1=Daniel B |title=The Segment:Offset Addressing Scheme |url=https://thestarman.pcministry.com/asm/debug/Segments.html |website=thestarman.pcministry.com |access-date=6 March 2025 |archive-date=10 March 2025 |archive-url=https://web.archive.org/web/20250310003121/https://thestarman.pcministry.com/asm/debug/Segments.html |url-status=live }}</ref> | ||
{| style="margin-left:5em" | {| style="margin-left:5em" | ||
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Compilers for the 8086 family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address. | Compilers for the 8086 family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address. | ||
{{See also|x86 memory models}} | |||
To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]'' files for instance. Precompiled libraries often come in several versions compiled for different memory models. | To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]'' files for instance. Precompiled libraries often come in several versions compiled for different memory models. | ||
According to Morse et al.,.<ref>{{cite journal |first1=Stephen P. |last1=Morse |first2=Bruce W |last2=Ravenel |first3=Stanley |last3=Mazor |first4=William B. |last4=Pohlman |title=Intel Microprocessors: 8008 to 8086 |journal=IEEE Computer |volume=13 |issue=10 |pages=42–60 |date=October 1980 |doi=10.1109/MC.1980.1653375 |s2cid=206445851 |url=https://stevemorse.org/8086history/8086history.doc|url-access=subscription }}</ref> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins. | According to Morse et al.,.<ref>{{cite journal |first1=Stephen P. |last1=Morse |first2=Bruce W |last2=Ravenel |first3=Stanley |last3=Mazor |first4=William B. |last4=Pohlman |title=Intel Microprocessors: 8008 to 8086 |journal=IEEE Computer |volume=13 |issue=10 |pages=42–60 |date=October 1980 |doi=10.1109/MC.1980.1653375 |s2cid=206445851 |url=https://stevemorse.org/8086history/8086history.doc |url-access=subscription |archive-date=2022-10-27 |access-date=2022-10-27 |archive-url=https://web.archive.org/web/20221027234658/https://stevemorse.org/8086history/8086history.doc |url-status=live }}</ref> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins. | ||
In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way. | In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way. | ||
The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of the instruction stream to be queued while waiting for decoding and execution. The queue acts as a | The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of the instruction stream to be queued while waiting for decoding and execution. The queue acts as a [[FIFO (electronic)|first-in-first-out]] (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.<ref name="8086Datasheet">{{cite web |title=8086 16-BIT HMOS Processor datasheet |url=https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf |publisher=Intel |access-date=26 November 2021 |archive-date=26 November 2021 |archive-url=https://web.archive.org/web/20211126175101/https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf |url-status=dead }}</ref> | ||
====Porting older software==== | ====Porting older software==== | ||
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===Interrupts=== | ===Interrupts=== | ||
[[Interrupt | [[Image:X86 Interrupt Vector Table.svg|thumb|Format of the 8086's interrupt vector table]] | ||
There are three types of software | [[Interrupt]]s on the 8086 can be either software or hardware-initiated. Interrupts are long calls that also save the processor status. Interrupt routines typically end with a <code>IRET</code> instruction. All interrupts have a 8-bit interrupt number associated with them. This number is used to look up a segment:offset in a 256 element [[interrupt vector table]] stored at addresses 0-3FFH. When any type of interrupt is encountered, the processor status is pushed, CS and IP are pushed, and the interrupt number is multiplied by four to index a new execution address which is loaded from the vector table. | ||
There are three types of software [[INT (x86 instruction)|interrupt instructions]]: <code>INT n</code>, <code>INTO</code>, and a single-byte <code>INT 3</code> used for debugging. | |||
There are two kinds of hardware interrupts: maskable and non-maskable. | There are two kinds of hardware interrupts: maskable and non-maskable. | ||
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'''Non-maskable''' interrupts are higher priority than maskable interrupts. They cannot be disabled by interrupt enable. A low to high transition on the NMI pin essentially causes an <code>INT 2</code> to execute. | '''Non-maskable''' interrupts are higher priority than maskable interrupts. They cannot be disabled by interrupt enable. A low to high transition on the NMI pin essentially causes an <code>INT 2</code> to execute. | ||
'''Maskable''' interrupts are enabled and disabled by the <code>STI</code> and <code>CLI</code> instructions respectively. When the INTR is asserted by a hardware device, the 8086 asserts INTA twice, reading an 8-bit interrupt number from the bus. This number is multiplied by four to point to the associated interrupt service routine in the vector table. Maskable interrupts are disabled when INTA is asserted, but are re-enabled upon executing the <code>IRET</code> instruction at the end of the interrupt service routine.<ref name="8086Datasheet"></ref> | '''Maskable''' interrupts are enabled and disabled by the <code>STI</code> and <code>CLI</code> instructions respectively. When the INTR is asserted by a hardware device, the 8086 asserts INTA twice, reading an 8-bit interrupt number from the bus. This number is multiplied by four to point to the associated interrupt service routine address in the vector table. Maskable interrupts are disabled when INTA is asserted, but are re-enabled upon executing the <code>IRET</code> instruction at the end of the interrupt service routine.<ref name="8086Datasheet"></ref> | ||
== Example code == | == Example code == | ||
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[[File:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main & index registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']] | [[File:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main & index registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']] | ||
Although partly shadowed by other design choices in this particular chip, the [[multiplexed]] address and [[Bus (computing)|data buses]] limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made [[Concurrency (computer science)|concurrent]] and decoupled into separate units (as it remains in today's x86 processors): The ''bus interface unit'' feeds the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[Pipeline (computing)|pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations became slower (four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]] types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). | Although partly shadowed by other design choices in this particular chip, the [[multiplexed]] address and [[Bus (computing)|data buses]] limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made [[Concurrency (computer science)|concurrent]] and decoupled into separate units (as it remains in today's x86 processors): The ''bus interface unit'' feeds the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[Pipeline (computing)|pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations became slower (four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full-width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]] types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). | ||
{| class="wikitable" style="text-align: center; width: 100px; height: 50px;" | {| class="wikitable" style="text-align: center; width: 100px; height: 50px;" | ||
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| 0 °C to 70 °C<ref name="Intel Preview Special Issue 1980, page 29">{{cite journal |author=Intel Corporation |title=8086 Available for industrial environment |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=29 |oclc=803251993}}</ref> | | 0 °C to 70 °C<ref name="Intel Preview Special Issue 1980, page 29">{{cite journal |author=Intel Corporation |title=8086 Available for industrial environment |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=29 |oclc=803251993}}</ref> | ||
| | | | ||
| June 8, 1978<ref>{{Cite web|url=https://www.intel.com/pressroom/kits/quickrefyr.htm|title=Intel® Microprocessor Quick Reference Guide - Year|website=www.intel.com}}</ref> | | June 8, 1978<ref>{{Cite web|url=https://www.intel.com/pressroom/kits/quickrefyr.htm|title=Intel® Microprocessor Quick Reference Guide - Year|website=www.intel.com|access-date=2021-02-28|archive-date=2021-10-06|archive-url=https://web.archive.org/web/20211006020846/https://www.intel.com/pressroom/kits/quickrefyr.htm|url-status=live}}</ref> | ||
| $86.65<ref>{{cite journal |author=Intel Corporation |title=The 8086 Family: Concepts and realities |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=19 |issn=1041-8547 |oclc=10331599}}</ref> | | $86.65<ref>{{cite journal |author=Intel Corporation |title=The 8086 Family: Concepts and realities |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=19 |issn=1041-8547 |oclc=10331599}}</ref> | ||
|- | |- | ||
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* [[Intel 8288]]: bus controller | * [[Intel 8288]]: bus controller | ||
* [[Intel 8289]]: bus arbiter | * [[Intel 8289]]: bus arbiter | ||
* [[Floppy-disk controller|NEC μPD765 or Intel 8272A]]: floppy controller<!--also NE72065--><ref>{{cite web|title=The floppy controller evolution | OS/2 Museum |date=2011-05-26 |access-date=2016-05-12 |url=https://www.os2museum.com/wp/the-floppy-controller-evolution/ |quote=In the original IBM PC (1981) and PC/XT (1983), the FDC was physically located on a separate diskette adapter card. The FDC itself was a NEC μPD765A or a compatible part, such as the Intel 8272A.}}</ref> | * [[Floppy-disk controller|NEC μPD765 or Intel 8272A]]: floppy controller<!--also NE72065--><ref>{{cite web |title=The floppy controller evolution | OS/2 Museum |date=2011-05-26 |access-date=2016-05-12 |url=https://www.os2museum.com/wp/the-floppy-controller-evolution/ |quote=In the original IBM PC (1981) and PC/XT (1983), the FDC was physically located on a separate diskette adapter card. The FDC itself was a NEC μPD765A or a compatible part, such as the Intel 8272A. |archive-date=2016-05-05 |archive-url=https://web.archive.org/web/20160505233125/http://www.os2museum.com/wp/the-floppy-controller-evolution/ |url-status=live }}</ref> | ||
==Microcomputers using the 8086== | ==Microcomputers using the 8086== | ||
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* The [[Xerox NoteTaker]] was one of the earliest [[portable computer]] designs in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production. | * The [[Xerox NoteTaker]] was one of the earliest [[portable computer]] designs in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production. | ||
* [[Seattle Computer Products]] shipped [[S-100 bus]] based 8086 systems (SCP200B) as early as November 1979. | * [[Seattle Computer Products]] shipped [[S-100 bus]] based 8086 systems (SCP200B) as early as November 1979. | ||
* The Norwegian [[Mycron]] 2000, introduced in | * The Norwegian [[Mycron]] 2000, introduced in 1980s | ||
* The first [[Compaq Deskpro]] used an 8086 running at 7.16 MHz, but was compatible with add-in cards designed for the 4.77 MHz [[IBM PC XT]] and could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues. | * The first [[Compaq Deskpro]] used an 8086 running at 7.16 MHz, but was compatible with add-in cards designed for the 4.77 MHz [[IBM PC XT]] and could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues. | ||
* An 8 MHz 8086-2 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]], and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10 MHz. | * An 8 MHz 8086-2 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]], and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10 MHz. | ||
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* The [[Tandy 1000]] SL-series and RL machines used 9.47 MHz 8086 CPUs. | * The [[Tandy 1000]] SL-series and RL machines used 9.47 MHz 8086 CPUs. | ||
* The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982" >{{cite magazine | last = Zachmann | first = Mark | title = Flaws in IBM Personal Computer frustrate critic | magazine = [[InfoWorld]] | volume = 4 | issue = 33 | pages =57–58 | date = August 23, 1982 | url = https://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649 | quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.}}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086. | * The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982" >{{cite magazine | last = Zachmann | first = Mark | title = Flaws in IBM Personal Computer frustrate critic | magazine = [[InfoWorld]] | volume = 4 | issue = 33 | pages =57–58 | date = August 23, 1982 | url = https://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649 | quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.}}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086. | ||
* [[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>{{cite news |url=https://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 |title=For Old Parts, NASA Boldly Goes ... on eBay |date=May 12, 2002 |newspaper=New York Times |url-access=limited}}</ref> | * [[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>{{cite news |url=https://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 |title=For Old Parts, NASA Boldly Goes ... on eBay |date=May 12, 2002 |newspaper=New York Times |url-access=limited |archive-date=June 29, 2016 |access-date=February 19, 2017 |archive-url=https://web.archive.org/web/20160629175355/http://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 |url-status=live }}</ref> | ||
* KAMAN Process and Area Radiation Monitors<ref>Kaman Tech. Manual</ref> | * KAMAN Process and Area Radiation Monitors<ref>Kaman Tech. Manual</ref> | ||
* The [[Tektronix]] 4170 ran [[CP/M-86]] and used an 8086 {{citation|url=https://bitsavers.org/pdf/tektronix/4170/061-2880-00_4170_Local_Graphics_Processing_Unit_Instruction_Manual_Apr1984.pdf|title=4170 Local Graphics Processing Unit Instruction Manual}} | * The [[Tektronix]] 4170 ran [[CP/M-86]] and used an 8086 {{citation|url=https://bitsavers.org/pdf/tektronix/4170/061-2880-00_4170_Local_Graphics_Processing_Unit_Instruction_Manual_Apr1984.pdf|title=4170 Local Graphics Processing Unit Instruction Manual}} | ||
One of the most influential microcomputers of all, the [[IBM PC]], used the [[Intel 8088]], a version of the 8086 with an 8-bit [[Bus (computing)|data bus]]. | |||
==See also== | ==See also== | ||
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* [https://web.archive.org/web/20140821053853/http://www.shubhsblog.com/category/8086-programs/ 8086 program codes using emu8086 (Version 4.08) Emulator] | * [https://web.archive.org/web/20140821053853/http://www.shubhsblog.com/category/8086-programs/ 8086 program codes using emu8086 (Version 4.08) Emulator] | ||
* {{cite web |first=Andrew |last=Jenner |title=8086 microcode disassembled |date=September 2020 |work=Reenigne blog |url=https://www.reenigne.org/blog/8086-microcode-disassembled/}} | * {{cite web |first=Andrew |last=Jenner |title=8086 microcode disassembled |date=September 2020 |work=Reenigne blog |url=https://www.reenigne.org/blog/8086-microcode-disassembled/}} | ||
* {{cite web |first=Ken |last=Shirriff |title=A look at the die of the 8086 processor |date=June 2020 |url=https://www.righto.com/2020/06/a-look-at-die-of-8086-processor.html}} | * {{cite web |first=Ken |last=Shirriff |title=A look at the die of the 8086 processor |date=June 2020 |url=https://www.righto.com/2020/06/a-look-at-die-of-8086-processor.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Die shrink: How Intel scaled down the 8086 processor |date=June 2020 |url=https://www.righto.com/2020/06/die-shrink-how-intel-scaled-down-8086.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The Intel 8086 processor's registers: from chip to transistors |date=July 2020 |url=https://www.righto.com/2020/07/the-intel-8086-processors-registers.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the adder inside the Intel 8086 |date=August 2020 |url=https://www.righto.com/2020/08/reverse-engineering-adder-inside-intel.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the 8086's Arithmetic/Logic Unit from die photos |date=August 2020 |url=https://www.righto.com/2020/08/reverse-engineering-8086s.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The unusual bootstrap drivers inside the 8086 microprocessor chip |date=November 2022 |url=https://www.righto.com/2022/11/the-unusual-bootstrap-drivers-inside.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=A bug fix in the 8086 microprocessor, revealed in the die's silicon |date=November 2022 |url=https://www.righto.com/2022/11/a-bug-fix-in-8086-microprocessor.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=How the 8086 processor's microcode engine works |date=December 2022 |url=https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Inside the 8086 processor's instruction prefetch circuitry |date=January 2023 |url=https://www.righto.com/2023/01/inside-8086-processors-instruction.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The 8086 processor's microcode pipeline from die analysis |date=January 2023 |url=https://www.righto.com/2023/01/the-8086-processors-microcode-pipeline.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Counting the transistors in the 8086 processor: it's harder than you might think |date=January 2023 |url=https://www.righto.com/2023/01/counting-transistors-in-8086-processor.html}} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the conditional jump circuitry in the 8086 processor |date=January 2023 |url=https://www.righto.com/2023/01/reverse-engineering-conditional-jump.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the Intel 8086 processor's HALT circuits |date=January 2023 |url=https://www.righto.com/2023/01/reverse-engineering-intel-8086.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Understanding the x86's Decimal Adjust after Addition (DAA) instruction |date=January 2023 |url=https://www.righto.com/2023/01/understanding-x86s-decimal-adjust-after.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Silicon reverse-engineering: the Intel 8086 processor's flag circuitry |date=February 2023 |url=https://www.righto.com/2023/02/silicon-reverse-engineering-intel-8086.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the interrupt circuitry in the Intel 8086 processor |date=February 2023 |url=https://www.righto.com/2023/02/8086-interrupt.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the ModR/M addressing microcode in the Intel 8086 processor |date=February 2023 |url=https://www.righto.com/2023/02/8086-modrm-addressing.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=How the 8086 processor determines the length of an instruction |date=March 2023 |url=https://www.righto.com/2023/02/how-8086-processor-determines-length-of.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the multiplication algorithm in the Intel 8086 processor |date=March 2023 |url=http://www.righto.com/2023/03/8086-multiplication-microcode.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the register codes for the 8086 processor's microcode |date=March 2023 |url=http://www.righto.com/2023/03/8086-register-codes.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The microcode and hardware in the 8086 processor that perform string operations |date=April 2023 |url=http://www.righto.com/2023/04/8086-microcode-string-operations.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the division microcode in the Intel 8086 processor |date=April 2023 |url=http://www.righto.com/2023/04/reverse-engineering-8086-divide-microcode.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The Group Decode ROM: The 8086 processor's first step of instruction decoding |date=May 2023 |url=http://www.righto.com/2023/05/8086-processor-group-decode-rom.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the 8086 processor's address and data pin circuits |date=July 2023 |url=http://www.righto.com/2023/07/8086-pins.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Undocumented 8086 instructions, explained by the microcode |date=July 2023 |url=http://www.righto.com/2023/07/undocumented-8086-instructions.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Tracing the roots of the 8086 instruction set to the Datapoint 2200 minicomputer |date=August 2023 |url=http://www.righto.com/2023/08/datapoint-to-8086.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=A close look at the 8086 processor's bus hold circuitry |date=August 2023 |url=http://www.righto.com/2023/08/intel-8086-bus-hold.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=How flip-flops are implemented in the Intel 8086 processor |date=October 2023 |url=http://www.righto.com/2023/09/8086-flip-flops.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The Intel 8088 processor's instruction prefetch circuitry: a look inside |date=March 2024 |url=http://www.righto.com/2024/03/8088-prefetch-circuitry.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Talking to memory: Inside the Intel 8088 processor's bus interface state machine |date=April 2024 |url=http://www.righto.com/2024/04/intel-8088-bus-state-machine.html }} {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Notes on the Intel 8086 processor's arithmetic-logic unit |date=January 2026 |url=http://www.righto.com/2026/01/notes-on-intel-8086-processors.html}} | ||
{{Intel processors|discontinued}} | {{Intel processors|discontinued}} | ||
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[[Category:Computer-related introductions in 1978]] | [[Category:Computer-related introductions in 1978]] | ||
[[Category:X86 microarchitectures]] | [[Category:X86 microarchitectures]] | ||
[[Category:Products and services discontinued in 1998]] | |||