Itanium: Difference between revisions

Line 5:

| image=Intel Itanium logo.svg

| image_size = 150px

| caption=

| caption=Logo from 2006 to 2009

| produced-start={{start date and age|2001|06}}{{Efn|Itanium was launched on 29 May,<ref>{{cite web |title=Intel officially launches 64-bit Itanium chip |url=https://www.computerworld.com/article/2582076/intel-officially-launches-64-bit-itanium-chip.html |website=[[Computerworld]] |date=29 May 2001}}</ref><ref>{{cite web |last1=Fordahl |first1=Matthew |title=Intel, HP Launch New Processor |url=https://abcnews.go.com/Technology/story?id=98536&page=1 |website=[[ABC News (United States)|ABC News]] |date=30 May 2001}}</ref><ref>{{cite web |last1=Bekker |first1=Scott |title=Intel Launches Itanium: OEMs Unveil Systems |url=https://rcpmag.com/articles/2001/05/29/intel-launches-itanium-oems-unveil-systems.aspx |website=RCP Mag |date=29 May 2001}}</ref><ref>{{cite web |last1=Kerridge |first1=Suzanna |title=Intel opens up about forthcoming Itanium family |url=https://www.zdnet.com/article/intel-opens-up-about-forthcoming-itanium-family/ |website=[[ZDNet]] |date=18 May 2001}}</ref> but the computers containing it shipped to customers in June.}}

| produced-end={{end date and age|2020|01|30}}<ref name="theend">{{cite web|url=https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf|title=Select Intel Itanium Processors and Intel Scalable Memory Buffer, PCN 116733-00, Product Discontinuance, End of Life|date=January 30, 2019|publisher=Intel|access-date=May 20, 2020|archive-date=May 22, 2020|archive-url=https://web.archive.org/web/20200522180927/https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf|url-status=live}} (January 30, 2020 was the last date for placing an order, all shipped no later than July 29, 2021).</ref>

Line 24:

| l3cache=Up to 32 MB

| soldby=[[Intel]]

| designfirm=Intel Hewlett-Packard

| designfirm=Intel [[Hewlett-Packard]]

|model1=Itanium|model2=Itanium 2|model3=Itanium 9000 series|core1=Merced|core2=McKinley|core3=Madison 3M/6M/9M|core4=Deerfield (Madison LV)|core5=Hondo{{efn|Hondo is an HP product, not an Intel product}}|core6=Fanwood (Madison DP)|core7=Montecito|core8=Montvale|core9=Tukwila|core10=Poulson|qpi-slowest=4.8|qpi-fastest=6.4|sock1=[[PAC 418]]|sock2=[[PAC 611]]|sock3=[[LGA 1248]]|model4=Itanium 9100 series|model5=Itanium 9300 series|model6=Itanium 9500 series|model7=Itanium 9700 series|l1cache=Up to 32 KB per core (data) Up to 32 KB per core (instructions)|l4cache=32 MB (Hondo only)|application=High-end/[[Mission critical|mission critical servers]] [[High performance computing]] High-end workstations|data-width=64 bits|address-width=64 bits|virtual-width=64 bits|microarch=P7|core11=~~Kittison~~|extensions1=[[SpeedStep|EIST]], [[VT-x]], [[VT-d]], [[VT-i]]|pack1=Pin Array Cartridge (PAC)|pack2=[[Flip-chip]] [[land grid array]] (FC-LGA)|support_status=Unsupported|amountmemory=Up to 1.5 TB|memory1=Up to [[DDR3 SDRAM|DDR3]] with [[Error correction code|ECC]] support}}

|model1=Itanium|model2=Itanium 2|model3=Itanium 9000 series|core1=Merced|core2=McKinley|core3=Madison 3M/6M/9M|core4=Deerfield (Madison LV)|core5=Hondo{{efn|Hondo is an HP product, not an Intel product}}|core6=Fanwood (Madison DP)|core7=Montecito|core8=Montvale|core9=Tukwila|core10=Poulson|qpi-slowest=4.8|qpi-fastest=6.4|sock1=[[PAC 418]]|sock2=[[PAC 611]]|sock3=[[LGA 1248]]|model4=Itanium 9100 series|model5=Itanium 9300 series|model6=Itanium 9500 series|model7=Itanium 9700 series|l1cache=Up to 32 KB per core (data) Up to 32 KB per core (instructions)|l4cache=32 MB (Hondo only)|application=High-end/[[Mission critical|mission critical servers]] [[High performance computing]] High-end workstations|data-width=64 bits|address-width=64 bits|virtual-width=64 bits|microarch=P7|core11=Kittson|extensions1=[[SpeedStep|EIST]], [[VT-x]], [[VT-d]], [[VT-i]]|pack1=Pin Array Cartridge (PAC)|pack2=[[Flip-chip]] [[land grid array]] (FC-LGA)|support_status=Unsupported|amountmemory=Up to 1.5 TB|memory1=Up to [[DDR3 SDRAM|DDR3]] with [[Error correction code|ECC]] support}}

'''Itanium''' ({{IPAc-en|aɪ|ˈ|t|eɪ|n|i|ə|m}}; {{respell|eye|TAY|nee-əm}}) is a discontinued family of [[64-bit computing|64-bit]] [[Intel]] [[microprocessor]]s that implement the [[Intel Itanium architecture]] (formerly called IA-64). The Itanium architecture originated at [[Hewlett-Packard]] (HP), and was later jointly developed by HP and Intel. Launching in June 2001, Intel initially marketed the processors for [[enterprise server]]s and [[high-performance computing]] systems. In the concept phase, engineers said "we could run circles around PowerPC...we could kill the x86". Early predictions were that IA-64 would expand to the lower-end servers, supplanting [[Xeon]], and eventually penetrate into the [[personal computer]]s, eventually to supplant [[Reduced instruction set computer|reduced instruction set computing]] (RISC) and [[complex instruction set computing]] (CISC) architectures for all general-purpose applications.

'''Itanium''' ({{IPAc-en|aɪ|ˈ|t|eɪ|n|i|ə|m}}; {{respell|eye|TAY|nee-əm}}) is a discontinued family of [[64-bit computing|64-bit]] [[Intel]] [[microprocessor]]s that implement the [[Intel Itanium architecture]] (formerly called IA-64). The Itanium architecture originated at [[Hewlett-Packard]] (HP), and was later jointly developed by HP and Intel. Launching in June 2001, Intel initially marketed the processors for [[enterprise server]]s and [[high-performance computing]] systems. In the concept phase, engineers said "we could run circles around [[PowerPC]]...we could kill the x86". Early predictions were that IA-64 would expand to the lower-end servers, supplanting [[Xeon]], and eventually penetrate into the [[personal computer]]s, eventually to supplant [[Reduced instruction set computer|reduced instruction set computing]] (RISC) and [[complex instruction set computing]] (CISC) architectures for all general-purpose applications.

When first released in 2001 after a decade of development, Itanium's performance was disappointing compared to better-established RISC and CISC processors. Emulation to run existing x86 applications and operating systems was particularly poor. Itanium-based systems were produced by HP and its successor [[Hewlett Packard Enterprise]] (HPE) as the [[HPE Integrity Servers|Integrity Servers]] line, and by several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for [[Enterprise information system|enterprise-class systems]], behind [[x86-64]], [[Power ISA]], and [[SPARC]].<ref name="ITJungle">{{cite web

When first released in 2001 after a decade of development, Itanium's performance was disappointing compared to better-established [[RISC]] and [[Complex instruction set computer|CISC]] processors. Emulation to run existing x86 applications and operating systems was particularly poor. Itanium-based systems were produced by HP and its successor [[Hewlett Packard Enterprise]] (HPE) as the [[HPE Integrity Servers|Integrity Servers]] line, and by several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for [[Enterprise information system|enterprise-class systems]], behind [[x86-64]], [[Power ISA]], and [[SPARC]].<ref name="ITJungle">{{cite web

|url = http://www.itjungle.com/tlb/tlb052708-story03.html

|title = The Server Biz Enjoys the X64 Upgrade Cycle in Q1

Line 41:

|work = IT Jungle

|df = mdy-all

}}</ref>~~{{Update inline|reason=That's 9 years old, although it's probably still true, unless it's now behind z/Architecture as well.|date=April 2017}}~~

}}</ref>

In February 2017, Intel released the final generation, Kittson, to test customers, and in May began shipping in volume.<ref name="Davis 2017">{{cite web

Line 85:

}}</ref> In 1993 HP held an internal competition to design the best (simulated) microarchitectures of a RISC and an EPIC type, led by Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] respectively. The EPIC team won, with over double the simulated performance of the RISC competitor.<ref name="nyt_merced">{{cite web |last1=Markoff |first1=John |title=Inside Intel, The Future is Riding on the Merced Chip |url=https://archive.org/details/TheJerusalemPost1998IsraelEnglish/Apr%2006%201998%2C%20The%20Jerusalem%20Post%2C%20%2319898%2C%20Israel%20%28en%29/page/n12/mode/1up |publisher=[[The New York Times]], republised by [[The Jerusalem Post]] |date=5 April 1998}}</ref>

At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>

At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium, too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>

In November 1993 HP approached Intel, seeking collaboration on an innovative future architecture.<ref name="countdown">{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}}</ref>{{refn|{{cite web |last1=Alpert |first1=Donald |title=Intel Itanium Processor (Merced) |url=https://camelback-comparch.com/about/technical-highlights/#merced |date=July 2003}} Alpert was the chief architect of the original P7 and the top engineering manager of Merced<ref>{{cite web |last1=Smotherman |first1=Mark |title=Who are the Computer Architects? |url=https://people.computing.clemson.edu/~mark/architects.html |publisher=[[Clemson University]] }} See the sections "Independence architecture" and "Wintel".</ref>}} At the time Intel was looking to extend x86 to 64 bits in a processor codenamed P7, which they found challenging.<ref>{{cite web |last1=DeMone |first1=Paul |title=What's Up With Willamette? (Part 1) |url=https://www.realworldtech.com/willamette-basics/ |website=Real World Tech |date=3 March 2000}}</ref> Later Intel claimed that four different design teams had explored 64-bit extensions, but each of them concluded that it was not economically feasible.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel takes slow road to 64-bit PC chips |url=https://www.cnet.com/tech/tech-industry/intel-takes-slow-road-to-64-bit-pc-chips/ |website=[[CNET]] |date=21 February 2003}}</ref> At the meeting with HP, Intel's engineers were impressed when Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] presented the PA-WideWord architecture they had designed to replace [[PA-RISC]]. "When we saw WideWord, we saw a lot of things we had only been looking at doing, already in their full glory", said Intel's [[John Crawford (engineer)|John Crawford]], who in 1994 became the chief architect of Merced, and who had earlier argued against extending the x86 with P7. HP's Gupta recalled: "I looked Albert Yu [Intel's general manager for microprocessors] in the eyes and showed him we could run circles around [[PowerPC]], that we could kill PowerPC, that we could kill the x86."<ref name="gambles"/> Soon Intel and HP started conducting in-depth technical discussions at an HP office, where each side had six{{Refn|<ref name="countdown"/><ref name="birth">{{cite web |last1=Britt |first1=Russ |title=The birth of a new processor |url=https://www.edn.com/the-birth-of-a-new-processor/ |website=[[EDN (magazine)|EDN]] |date=1 January 2000}}</ref> (The {{Define|ACM|architecture, compilers, microarchitecture}} committee with 5 people from each side<ref>{{cite web |last1=Smotherman |first1=Mark |title=Historical background for EPIC instruction set architectures |url=https://people.computing.clemson.edu/~mark/epic.html |publisher=[[Clemson University]] |access-date=3 June 2022}}</ref> was probably a different entity.)}} engineers who exchanged and discussed both companies' confidential architectural research. They then decided to use not only PA-WideWord, but also the more experimental [[HP Labs]] PlayDoh as the source of their joint future architecture.<ref name="simplicity">{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/ |website=Real World Tech |date=27 October 1999}}</ref><ref>{{cite web |last1=Kathail |first1=Vinod |last2=Schlansker |first2=Michael S. |last3=Rau |first3=B. Ramakrishna |title=HPL-PD Architecture Specification: Version 1.1 |url=https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |publisher=[[HP Labs|HP Laboratories]] |access-date=2023-07-05 |archive-date=2024-02-04 |archive-url=https://web.archive.org/web/20240204063521/https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |url-status=dead }}</ref> Convinced of the superiority of the new project, in 1994 Intel canceled their existing plans for P7.

Line 136:

| archive-date=May 3, 2012

| archive-url=https://web.archive.org/web/20120503094946/http://www.anandtech.com/show/1854

| url-status=~~live~~

| url-status=dead

}}</ref><ref name="Venturebeat">{{cite web

| url=https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/

Line 160:

}}</ref>

Several groups ported operating systems for the architecture, including [[Microsoft Windows]], [[OpenVMS]], [[Linux]], [[HP-UX]], [[Solaris ~~(operating system)~~|Solaris]],<ref name="Solaris-Merced1">{{cite web

Several groups ported operating systems for the architecture, including [[Microsoft Windows]], [[OpenVMS]], [[Linux]], [[HP-UX]], [[Oracle Solaris|Solaris]],<ref name="Solaris-Merced1">{{cite web

| url=http://www.computerworld.com/home/news.nsf/all/9909013sunsol

| title=Solaris for IA-64 coming this fall

Line 199:

| date=October 4, 1999

| website=[[CNET]]

}}</ref>

}}</ref> Within hours, the name '''''Itanic''''' had been coined on a [[Usenet]] newsgroup, a reference to the [[RMS Titanic|RMS ''Titanic'']], the "unsinkable" [[ocean liner]] that sank on her maiden voyage in 1912.<ref>{{cite newsgroup

Within hours, the name '''''Itanic''''' had been coined on a [[Usenet]] newsgroup, a reference to the [[RMS Titanic|RMS ''Titanic'']], the "unsinkable" [[ocean liner]] that sank on her maiden voyage in 1912.<ref>{{cite newsgroup

| url=https://groups.google.com/d/msg/comp.sys.mac.advocacy/UiOOaXF3-lI/f3nje9CHPx0J

| title=Re:Itanium

Line 274:

Line 273:

| archive-url=https://web.archive.org/web/20191217201629/https://www.eetimes.com/itanium-era-dawns/

| url-status=live

}}</ref>

}}</ref> Itanium competed at the low-end (primarily four-[[central processing unit|CPU]] and smaller systems) with servers based on [[x86]] processors, and at the high-end with [[IBM Power microprocessors|IBM POWER]] and [[Sun Microsystems]] [[SPARC]] processors. Intel repositioned Itanium to focus on the high-end business and [[High-performance computing|HPC]] computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the [[PA-RISC]] in HP systems, [[DEC Alpha|Alpha]] in Compaq systems and [[MIPS architecture|MIPS]] in [[Silicon Graphics|SGI]] systems, though IBM also delivered a supercomputer based on this processor.<ref name="Thunder">{{cite web

Itanium competed at the low-end (primarily four-[[central processing unit|CPU]] and smaller systems) with servers based on [[x86]] processors, and at the high-end with [[IBM Power microprocessors|IBM POWER]] and [[Sun Microsystems]] [[SPARC]] processors. Intel repositioned Itanium to focus on the high-end business and [[High-performance computing|HPC]] computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the [[PA-RISC]] in HP systems, [[DEC Alpha|Alpha]] in Compaq systems and [[MIPS architecture|MIPS]] in [[Silicon Graphics|SGI]] systems, though IBM also delivered a supercomputer based on this processor.<ref name="Thunder">{{cite web

| url=http://www.top500.org/system/ranking/5597

| title=Titan Cluster Itanium 800 MHz

Line 293:

Line 291:

| date=December 11, 2001

| access-date=July 4, 2023

}}</ref> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.

}}</ref> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.{{clarify|reason=confusingly written sentence|date=December 2025}}

=== Itanium 2 (McKinley and Madison): 2002–2006 ===

Line 337:

Line 335:

The '''Itanium 2''' processor was released in July 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium 2, code-named ''McKinley'', was jointly developed by HP and Intel, led by the HP team at [[Fort Collins, Colorado]], [[tape-out|taping out]] in December 2000. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem by approximately halving the latency and doubling the fill bandwidth of each of the three levels of cache, while expanding the L2 cache from 96 to 256 KB. Floating-point data is excluded from the L1 cache, because the L2 cache's higher bandwidth is more beneficial to typical floating-point applications than low latency. The L3 cache is now integrated on-chip rather than on a separate die, tripling in associativity and doubling in bus width. McKinley also greatly increases the number of possible instruction combinations in a VLIW-bundle and reaches 25% higher frequency, despite having only eight pipeline stages versus Merced's ten.<ref>{{cite web |last1=Hammond |first1=Gary |last2=Naffziger |first2=Sam |title=Next Generation Itanium™ Processor Overview |url=http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-url=https://web.archive.org/web/20030706123550/http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-date=6 July 2003 |url-status=dead}}</ref><ref name="HP_McKinley_wp"/>

''McKinley'' contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5 mm by 21.6 mm (421 mm2) and was fabricated in a 180 nm, bulk CMOS process with six layers of aluminium metallization.<ref>{{cite journal |last1=Naffzinger |first1=Samuel D. |first2=Glenn T. |last2=Colon-Bonet |first3=Timothy |last3=Fischer |first4=Reid |last4=Riedlinger |first5=Thomas J. |last5=Sullivan |first6=Tom |last6=Grutkowski |date=November 2002 |title=The implementation of the Itanium 2 microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=37 |issue=11 |pages=1448–1460 |doi=10.1109/JSSC.2002.803943 |bibcode=2002IJSSC..37.1448N |url=http://cpus.hp.com/technical_references/jssc_naffziger.pdf|archive-url=https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf |archive-date=2003-03-22 |url-status=dead}}</ref><ref>{{cite web |last1=Soltis |first1=Don |last2=Gibson |first2=Mark |title=Itanium® 2 Processor Microarchitecture Overview |url=http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |website=[[Hot Chips]] |archive-url=https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |archive-date=31 May 2005 |url-status=dead}}</ref><ref>{{cite web |last1=Naffziger |first1=Samuel |last2=Hammond |first2=Gary |title=The Implementation of the Next-Generation 64b Itanium Microprocessor |url=http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-url=https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-date=29 October 2004 |url-status=dead}}</ref> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency to 800 MHz.<ref>{{cite web |last1=Krazit |first1=Tom |title=Intel details Itanium 2 bug |url=https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html |website=[[Computerworld]] |date=12 May 2003 |access-date=30 March 2022}}</ref>

''McKinley'' contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5 mm by 21.6 mm (421 mm2) and was fabricated in a 180 nm, bulk CMOS process with six layers of aluminium metallization.<ref>{{cite journal |last1=Naffzinger |first1=Samuel D. |first2=Glenn T. |last2=Colon-Bonet |first3=Timothy |last3=Fischer |first4=Reid |last4=Riedlinger |first5=Thomas J. |last5=Sullivan |first6=Tom |last6=Grutkowski |date=November 2002 |title=The implementation of the Itanium 2 microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=37 |issue=11 |pages=1448–1460 |doi=10.1109/JSSC.2002.803943 |bibcode=2002IJSSC..37.1448N |url=http://cpus.hp.com/technical_references/jssc_naffziger.pdf|archive-url=https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf |archive-date=2003-03-22 |url-status=dead}}</ref><ref>{{cite web |last1=Soltis |first1=Don |last2=Gibson |first2=Mark |title=Itanium® 2 Processor Microarchitecture Overview |url=http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |website=[[Hot Chips]] |archive-url=https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |archive-date=31 May 2005 |url-status=dead}}</ref><ref>{{cite web |last1=Naffziger |first1=Samuel |last2=Hammond |first2=Gary |title=The Implementation of the Next-Generation 64b Itanium Microprocessor |url=http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-url=https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-date=29 October 2004 |url-status=dead}}</ref> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency from the original 1 GHz to 800 MHz.<ref>{{cite web |last1=Krazit |first1=Tom |title=Intel details Itanium 2 bug |url=https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html |website=[[Computerworld]] |date=12 May 2003 |access-date=30 March 2022}}</ref>

In 2003, [[~~Advanced Micro Devices|~~AMD]] released the [[Opteron]] CPU, which implements its own [[64-bit computing|64-bit]] architecture called [[AMD64]]. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from [[x86]]. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 [[instruction set architecture]] instead of IA-64 in its [[Xeon]] microprocessors in 2004, resulting in a new industry-wide ''de facto'' standard.<ref name="cautionary"/>

In 2003, [[AMD]] released the [[Opteron]] CPU, which implements its own [[64-bit computing|64-bit]] architecture called [[X86-64#AMD64|AMD64]]. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from [[x86]]. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 [[instruction set architecture]] (instead of IA-64) in its [[Xeon]] microprocessors in 2004, resulting in a new industry-wide ''de facto'' standard.<ref name="cautionary"/>

In 2003, Intel released a new Itanium 2 family member, codenamed ''Madison'', initially with up to 1.5 GHz frequency and 6 MB of L3 cache. The ''Madison 9M'' chip released in November 2004 had 9 MB of L3 cache and frequency up to 1.6 GHz, reaching 1.67 GHz in July 2005. Both chips used a 130 nm process and were the basis of all new Itanium processors until Montecito was released in July 2006, specifically ''Deerfield'' being a low wattage ''Madison'', and ''Fanwood'' being a version of ''Madison 9M'' for lower-end servers with one or two CPU sockets.

Line 406:

Line 404:

}}

In early 2003, due to the success of IBM's dual-core [[POWER4]], Intel announced that the first [[90 nm]] Itanium processor, codenamed ''Montecito'', would be delayed to 2005 so as to change it into a dual-core, thus merging it with the ''Chivano'' project.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel accelerates Itanium schedule |url=https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref name="qa">{{cite news |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel's summer of servers |url=https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/ |website=[[The Globe and Mail]] |date=9 July 2003 |access-date=27 April 2022}}</ref> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of [[hyper-threading]] increases Montecito's performance by 10-20% and that its frequency could reach 2 GHz.<ref name="monty">{{cite web |last1=Kanellos |first1=Michael |title=Intel fills in more details on Itanium family |url=https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref>{{cite web |last1=Wilson |first1=Derek |title=Intel Developer Forum Fall 2004: Day 1 Keynote |url=https://www.anandtech.com/show/1465/3 |website=[[AnandTech]] |access-date=28 April 2022}}</ref> After a delay to "mid-2006" and reduction of the frequency to 1.6 GHz,<ref>{{cite news |last1=Shankland |first1=Stephen |title=Intel pushes back Itanium chips, revamps Xeon |url=https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/ |website=[[CNET]] |access-date=3 April 2022}}</ref> on July 18 Intel delivered ''Montecito'' (marketed as the '''Itanium 2 9000''' series), a [[multi-core processor|dual-core]] processor with a [[Multithreading (computer architecture)#Coarse-grained multithreading|switch-on-event multithreading]] and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<ref name="CW1">{{cite web

In early 2003, due to the success of IBM's dual-core [[POWER4]], Intel announced that the first [[90 nm]] Itanium processor, codenamed ''Montecito'', would be delayed to 2005 so as to change it into a dual-core, thus merging it with the ''Chivano'' project.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel accelerates Itanium schedule |url=https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref name="qa">{{cite news |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel's summer of servers |url=https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/ |website=[[The Globe and Mail]] |date=9 July 2003 |access-date=27 April 2022}}</ref> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of [[hyper-threading]] increases Montecito's performance by 10-20% and that its frequency could reach 2 GHz.<ref name="monty">{{cite web |last1=Kanellos |first1=Michael |title=Intel fills in more details on Itanium family |url=https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref>{{cite web |last1=Wilson |first1=Derek |title=Intel Developer Forum Fall 2004: Day 1 Keynote |url=https://www.anandtech.com/show/1465/3 |archive-url=https://web.archive.org/web/20210917112245/https://www.anandtech.com/show/1465/3 |url-status=dead |archive-date=September 17, 2021 |website=[[AnandTech]] |access-date=28 April 2022}}</ref> After a delay to "mid-2006" and reduction of the frequency to 1.6 GHz,<ref>{{cite news |last1=Shankland |first1=Stephen |title=Intel pushes back Itanium chips, revamps Xeon |url=https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/ |website=[[CNET]] |access-date=3 April 2022}}</ref> on July 18 Intel delivered ''Montecito'' (marketed as the '''Itanium 2 9000''' series), a [[multi-core processor|dual-core]] processor with a [[Multithreading (computer architecture)#Coarse-grained multithreading|switch-on-event multithreading]] and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<ref name="CW1">{{cite web

|url = https://www.computerworld.com/article/2536018/-tukwila--itanium-servers-due-early-next-year--intel-says.html

|title = 'Tukwila' Itanium servers due early next year, Intel says

Line 467:

Line 466:

| name=9500 and 9700 series

| produced-start=8 November 2012

| produced-end=30 January 2020<ref>{{cite web |last1=Shilov |first1=Anton |title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums |url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |website=[[AnandTech]] |access-date=28 April 2022}}</ref>

| produced-end=30 January 2020<ref>{{cite web |last1=Shilov |first1=Anton |title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums |url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |archive-url=https://web.archive.org/web/20190201050122/https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |url-status=dead |archive-date=February 1, 2019 |website=[[AnandTech]] |access-date=28 April 2022}}</ref>

| slowest=1.73

| fastest=2.67

Line 503:

Line 502:

[[File:Intel Itanium 9300 with cap removed.jpg|thumb|Intel Itanium 9300 with cap removed]]

The original code name for the first Itanium with more than two cores was Tanglewood, but it was changed to Tukwila in late 2003 due to trademark issues.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel changes code name of future Itanium |url=https://www.cnet.com/tech/tech-industry/intel-changes-code-name-of-future-itanium/ |website=[[CNET]] |access-date=4 July 2023}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Trademark flap prompts Intel to rename Tanglewood |url=https://www.infoworld.com/article/2678103/trademark-flap-prompts-intel-to-rename-tanglewood.html |website=[[InfoWorld]] |date=18 December 2003 |access-date=31 March 2022}}</ref> Intel discussed a "middle-of-the-decade Itanium" to succeed Montecito, achieving ten times the performance of Madison.<ref>{{cite news |last1=Vance |first1=Ashlee |author-link=Ashlee Vance |title=Tanglewood to run 10x faster than Madison |url=https://www.theregister.com/2003/05/01/tanglewood_to_run_10x_faster1/ |work=[[The Register]] |access-date=27 April 2022}}</ref><ref name="qa"/> It was being designed by the famed [[DEC Alpha]] team and was expected have eight new multithreading-focused cores. Intel claimed "a lot more than two" cores and more than seven times the performance of Madison.<ref>{{cite web |last1=McMillan |first1=Robert |title=FALL IDF: Intel readies 8-core, 16-core Itanium 2 |url=https://www.infoworld.com/article/2676169/fall-idf--intel-readies-8-core--16-core-itanium-2.html |website=[[InfoWorld]] |date=17 September 2003 |access-date=31 March 2022}}</ref><ref>{{cite web |last1=Shankland |first1=Stephen |title='Tanglewood' to top Intel chip show |url=https://www.cnet.com/tech/tech-industry/tanglewood-to-top-intel-chip-show/ |website=[[CNET]] |access-date=31 March 2022}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Itanium 2 Montecito to be multithreaded |url=https://www.computerweekly.com/news/2240053525/Itanium-2-Montecito-to-be-multithreaded |website=[[Computer Weekly]] |access-date=31 March 2022}}</ref> In early 2004 Intel told of "plans to achieve up to double the performance over the Intel Xeon processor family at platform cost parity by 2007".<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel}}</ref> By early 2005 Tukwila was redefined, now having fewer cores but focusing on single-threaded performance and multiprocessor scalability.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel to spotlight new Itanium: 'Poulson' |url=https://www.cnet.com/tech/tech-industry/intel-to-spotlight-new-itanium-poulson/ |website=[[CNET]] |access-date=31 March 2022}}</ref>

Line 589:

|archive-url = https://web.archive.org/web/20171201034615/http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf

|url-status = dead

}}</ref>

}}</ref> Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<ref>{{cite web

Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<ref>{{cite web

| url=https://www.realworldtech.com/poulson-preview/

| title=New Itanium Microarchitecture at ISSCC 2011

Line 599:

Line 598:

| work=Real World Tech

}}</ref>

Some information was also released at the [[Hot Chips]] conference.<ref>{{cite web

Some information was also released at the Hot Chips conference.<ref>{{cite web

|url = https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/

|title = Itanium Poulson Update — Greater Parallelism, New Instruction Replay & More: Catch the details from Hotchips!

Line 640:

Line 639:

|url-status = dead

|df = mdy-all

}}</ref>

}}</ref> The Poulson L3 cache size is 32 MB and common for all cores, not divided like previously. L2 cache size is 6 MB, 512 I [[Kibibyte|KB]], 256 D KB per core.<ref name="dx.doi.org">{{cite conference

The Poulson L3 cache size is 32 MB and common for all cores, not divided like previously. L2 cache size is 6 MB, 512 I [[Kibibyte|KB]], 256 D KB per core.<ref name="dx.doi.org">{{cite conference

| chapter=A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers

| date=February 24, 2011

Line 690:

Line 688:

In April 2015, Intel, although it had not yet confirmed formal specifications, did confirm that it continued to work on the project.<ref name=kitguru>{{cite web |url=https://www.kitguru.net/components/cpu/anton-shilov/intel-still-committed-to-make-new-itanium-processors/ |title=Intel still committed to make new Itanium processors |quote=KitGuru Says: Even though it is highly likely that "Kittson" chips will be released, it does not seem that Intel and HP actually want to invest R&D money in boosting performance of IA-64 chips. As a result, it looks like the best thing "Kittson" will offer will be a 20 per cent performance improvement over current gen offerings. |last1=Shilov |first1=Anton |date=April 17, 2015 |website=kitguru.net |access-date=July 4, 2023}}</ref> Meanwhile, the aggressively multicore Xeon E7 platform displaced Itanium-based solutions in the Intel roadmap.<ref>{{cite web |url=http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html |title=Intel's new Xeon server chip pushes Itanium closer to death's door |last1=Shah |first1=Agam |date=February 19, 2014 |website=pcworld.com |publisher=PC World |access-date=January 13, 2016 |archive-date=January 26, 2016 |archive-url=https://web.archive.org/web/20160126165249/http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html |url-status=live }}</ref> Even [[Hewlett-Packard]], the main proponent and customer for Itanium, began selling [[x86]]-based [[HP Superdome|Superdome]] and [[NonStop (server computers)|NonStop]] servers, and started to treat the Itanium-based versions as legacy products.<ref>{{cite web |last1=Shilov |first1=Anton |title=HP: mission-critical servers business improves as Itanium fades away |url=https://www.kitguru.net/professional/server/anton-shilov/hp-mission-critical-servers-business-improves-as-itanium-fades-away/ |website=Kitguru |access-date=30 March 2022}}</ref><ref>{{cite web |last1=Shah |first1=Agam |title=HP sees HP-UX sticking around for 10 years |url=https://www.computerworld.com/article/2853998/hp-sees-hp-ux-sticking-around-for-10-years.html |website=[[Computerworld]] |date=2 December 2014 |access-date=30 March 2022}}</ref>

Intel officially launched the '''Itanium 9700''' series processor family on May 11, 2017.<ref>{{cite web|title=Intel® Itanium® Processor|url=https://www-ssl.intel.com/content/www/us/en/products/processors/itanium.html|website=Intel|access-date=May 15, 2017}}</ref><ref name="IA-PCWorld"/> Kittson has no microarchitecture improvements over Poulson; despite nominally having a different stepping, it is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133 MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively.<ref>{{cite web |title=Intel® Itanium® Processor 9300, 9500 and 9700 Series Specification Update |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20201111234308/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |archive-date=11 November 2020 |url-status=live}}</ref><ref>{{cite news|last1=Cutress|first1=Ian|title=Intel's Itanium Takes One Last Breath: Itanium 9700 Series CPUs Released|url=http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|access-date=May 11, 2017|publisher=Anandtech|date=May 11, 2017|archive-date=May 11, 2017|archive-url=https://web.archive.org/web/20170511152533/http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|url-status=~~live~~}}</ref>

Intel officially launched the '''Itanium 9700''' series processor family on May 11, 2017.<ref>{{cite web|title=Intel® Itanium® Processor|url=https://www-ssl.intel.com/content/www/us/en/products/processors/itanium.html|website=Intel|access-date=May 15, 2017}}</ref><ref name="IA-PCWorld"/> Kittson has no microarchitecture improvements over Poulson; despite nominally having a different stepping, it is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133 MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively.<ref>{{cite web |title=Intel® Itanium® Processor 9300, 9500 and 9700 Series Specification Update |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20201111234308/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |archive-date=11 November 2020 |url-status=live}}</ref><ref>{{cite news|last1=Cutress|first1=Ian|title=Intel's Itanium Takes One Last Breath: Itanium 9700 Series CPUs Released|url=http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|access-date=May 11, 2017|publisher=Anandtech|date=May 11, 2017|archive-date=May 11, 2017|archive-url=https://web.archive.org/web/20170511152533/http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|url-status=dead}}</ref>

Intel announced that the 9700 series would be the last Itanium chips produced.<ref name="Davis 2017" /><ref name="IA-PCWorld" />

Line 722:

Line 720:

}}</ref>

According to [[Gartner Inc.]], the total number of Itanium servers (not processors) sold by all vendors in 2007, was about 55,000 (It is unclear whether clustered servers counted as a single server or not.). This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. [[International Data Corporation|IDC]] reports that a total of 184,000 Itanium-based systems were sold from 2001 through 2007. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% of revenue and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008.<ref>[[International Data Corporation|IDC]] World Wide Server Tracker, Q2'08</ref>

According to [[Gartner Inc.]], the total number of Itanium servers (not processors) sold by all vendors in 2007, was about 55,000 (it is unclear whether clustered servers counted as a single server or not). This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. [[International Data Corporation|IDC]] reports that a total of 184,000 Itanium-based systems were sold from 2001 through 2007. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% of revenue and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008.<ref>[[International Data Corporation|IDC]] World Wide Server Tracker, Q2'08</ref>

According to an IDC analyst, in 2007, HP accounted for perhaps 80% of Itanium systems revenue.<ref name="CW1"/>

According to Gartner, in 2008, HP accounted for 95% of Itanium sales.<ref name="vance late"/> HP's Itanium system sales were at an annual rate of $4.4Bn at the end of 2008, and declined to $3.5Bn by the end of 2009,<ref name="Gartner 2009-q4">{{cite news

Line 796:

Line 794:

}}</ref>

By 2015, only HP supplied Itanium-based systems.<ref name=kitguru/> When HP split in late 2015, Itanium systems (branded as [[HPE Integrity Servers|Integrity]])<ref name="eol">{{Cite web |last=Aleksandar |first=Kostovic |date=2021-07-31 |title=Itanium Waves Goodbye As Intel Delivers Last Shipments of Now Forgotten Processor Family |url=https://www.tomshardware.com/news/last-itanium-shipment |access-date=2022-11-29 |website=Tom's Hardware |language=en}}</ref> were handled by [[Hewlett Packard Enterprise]] (HPE), with a major update in 2017 (Integrity i6, and HP-UX 11i v3 Update 16). HPE also supports a few other operating systems, including [[Windows]] up to Server 2008 R2, [[Linux]], [[OpenVMS]] and [[NonStop (server computers)|NonStop]]. Itanium is not affected by [[Spectre (security vulnerability)|Spectre]] or [[Meltdown (security vulnerability)|Meltdown]].<ref>{{Cite news|url=https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|title=Not Vulnerable - Intel Itanium/Secure64 SourceT - Secure 64|date=January 9, 2018|work=Secure 64|access-date=October 4, 2018|language=en-US|archive-date=October 4, 2018|archive-url=https://web.archive.org/web/20181004103818/https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|url-status=live}}</ref>

By 2015, only HP supplied Itanium-based systems.<ref name=kitguru/> When HP split in late 2015, Itanium systems (branded as [[HPE Integrity Servers|Integrity]])<ref name="eol">{{Cite web |last=Aleksandar |first=Kostovic |date=2021-07-31 |title=Itanium Waves Goodbye As Intel Delivers Last Shipments of Now Forgotten Processor Family |url=https://www.tomshardware.com/news/last-itanium-shipment |access-date=2022-11-29 |website=Tom's Hardware |language=en}}</ref> were handled by [[Hewlett Packard Enterprise]] (HPE), with a major update in 2017 (Integrity i6, and HP-UX 11i v3 Update 16). HPE also supports a few other operating systems, including [[Windows]] up to Server 2008 R2, [[Linux]], [[OpenVMS]] and [[NonStop (server computers)|Tandem NonStop]]. Itanium is not affected by [[Spectre (security vulnerability)|Spectre]] or [[Meltdown (security vulnerability)|Meltdown]] security vulnerabilities.<ref>{{Cite news|url=https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|title=Not Vulnerable - Intel Itanium/Secure64 SourceT - Secure 64|date=January 9, 2018|work=Secure 64|access-date=October 4, 2018|language=en-US|archive-date=October 4, 2018|archive-url=https://web.archive.org/web/20181004103818/https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|url-status=live}}</ref>

=== Chipsets ===

Line 819:

Line 817:

The first generation of Itanium received no vendor-specific chipsets, only Intel's 460GX consisting of ten distinct chips. It supported up to four CPUs and 64 GB of memory at 4.2 GB/s, which is twice the system bus's bandwidth. Addresses and data were handled by two different chips. 460GX had an [[Accelerated Graphics Port|AGP]] X4 graphics bus, two 64-bit 66 MHz [[Peripheral Component Interconnect|PCI]] buses and configurable 33 MHz dual 32-bit or single 64-bit PCI bus(es).<ref>{{cite web |title=Intel 460GX Chipset Datasheet |url=http://developer.intel.com/design/itanium/downloads/24870301.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040723073549/http://developer.intel.com/design/itanium/downloads/24870301.pdf |archive-date=23 July 2004 |url-status=dead}}</ref>

There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E8870 chipset. It supports 128 GB of [[DDR SDRAM]] at 6.4 GB/s. It was originally designed for [[Rambus]] [[RDRAM]] [[serial communication|serial]] memory, but when RDRAM failed, Intel added four DDR SDRAM-to-RDRAM converter chips to the chipset.<ref>{{cite book |last1=Mueller |first1=Scott |last2=Soper |first2=Mark Edward |last3=Sosinsky |first3=Barrie |title=Upgrading and Repairing Servers |date=2006 |publisher=Pearson Education |isbn=0-13-279698-8 |url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT301 |access-date=6 April 2022}}</ref> When Intel had previously made such a converter for Pentium III chipsets 820 and 840, it drastically cut performance.<ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Intel's 820 Chipset - Performance using SDRAM |url=https://www.anandtech.com/show/465 |website=[[AnandTech]] |access-date=6 April 2022}}</ref><ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Rambus DRAM Part 2: Performance |url=https://www.anandtech.com/show/551 |website=[[AnandTech]] |access-date=6 April 2022}}</ref> E8870 provides eight 133 MHz [[PCI-X]] buses (4.2 GB/s total because of bottlenecks) and a [[I/O Controller Hub#ICH4|ICH4]] hub with six [[USB 2.0]] ports.

There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E8870 chipset. It supports 128 GB of [[DDR SDRAM]] at 6.4 GB/s. It was originally designed for [[Rambus]] [[RDRAM]] [[serial communication|serial]] memory, but when RDRAM failed, Intel added four DDR SDRAM-to-RDRAM converter chips to the chipset.<ref>{{cite book |last1=Mueller |first1=Scott |last2=Soper |first2=Mark Edward |last3=Sosinsky |first3=Barrie |title=Upgrading and Repairing Servers |date=2006 |publisher=Pearson Education |isbn=0-13-279698-8 |url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT301 |access-date=6 April 2022}}</ref> When Intel had previously made such a converter for Pentium III chipsets 820 and 840, it drastically cut performance.<ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Intel's 820 Chipset - Performance using SDRAM |url=https://www.anandtech.com/show/465 |archive-url=https://web.archive.org/web/20110729150352/http://www.anandtech.com/show/465 |url-status=dead |archive-date=July 29, 2011 |website=[[AnandTech]] |access-date=6 April 2022}}</ref><ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Rambus DRAM Part 2: Performance |url=https://www.anandtech.com/show/551 |archive-url=https://web.archive.org/web/20110419010747/http://www.anandtech.com/show/551 |url-status=dead |archive-date=April 19, 2011 |website=[[AnandTech]] |access-date=6 April 2022}}</ref> E8870 provides eight 133 MHz [[PCI-X]] buses (4.2 GB/s total because of bottlenecks) and a [[I/O Controller Hub#ICH4|ICH4]] hub with six [[USB 2.0]] ports.

Two E8870 can be linked together by two E8870SP Scalability Port Switches, each containing a 1MB (~200,000 cache lines) [[Bus snooping#Snoop filter|snoop filter]], to create an 8-socket system with double the memory and PCI-X capacity, but still only one ICH4. Further expansion to 16 sockets was planned.<ref>{{cite journal |display-authors=etal |last=Briggs |first=Fayé |title=Intel 870: a building block for cost-effective, scalable servers |journal=[[IEEE Micro]] |date=7 August 2002 |volume=22 |issue=2 (March–April) |pages=36–47 |doi=10.1109/MM.2002.997878 |citeseerx=10.1.1.140.2915 |s2cid=3201355 }}</ref><ref>{{cite web |title=Intel® E8870 Scalable Node Controller (SNC) Datasheet |url=http://www.intel.com/design/chipsets/datashts/25111203.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040701014149/http://www.intel.com/design/chipsets/datashts/25111203.pdf |archive-date=1 July 2004 |url-status=dead}}</ref><ref>{{cite web |title=Intel® E8870IO Server I/O Hub (SIOH) Datasheet |url=http://intel.com/design/chipsets/datashts/25111103.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20030706004227/http://intel.com/design/chipsets/datashts/25111103.pdf |archive-date=6 July 2003 |url-status=dead}}</ref> In 2004 Intel revealed plans for its next Itanium chipset, codenamed ''Bayshore'', to support [[PCI-e]] and [[DDR2 SDRAM|DDR2]] memory, but canceled it the same year.<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel |access-date=7 April 2022}}</ref><ref name="ibm_ditching_itanium"/>

Two E8870 can be linked together by two E8870SP Scalability Port Switches, each containing a 1MB (~200,000 cache lines) [[Bus snooping#Snoop filter|snoop filter]], to create an 8-socket system with double the memory and PCI-X capacity, but still only one ICH4. Further expansion to 16 sockets was planned.<ref>{{cite journal |display-authors=etal |last=Briggs |first=Fayé |title=Intel 870: a building block for cost-effective, scalable servers |journal=[[IEEE Micro]] |date=7 August 2002 |volume=22 |issue=2 (March–April) |pages=36–47 |doi=10.1109/MM.2002.997878 |bibcode=2002IMicr..22b..36B |citeseerx=10.1.1.140.2915 |s2cid=3201355 }}</ref><ref>{{cite web |title=Intel® E8870 Scalable Node Controller (SNC) Datasheet |url=http://www.intel.com/design/chipsets/datashts/25111203.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040701014149/http://www.intel.com/design/chipsets/datashts/25111203.pdf |archive-date=1 July 2004 |url-status=dead}}</ref><ref>{{cite web |title=Intel® E8870IO Server I/O Hub (SIOH) Datasheet |url=http://intel.com/design/chipsets/datashts/25111103.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20030706004227/http://intel.com/design/chipsets/datashts/25111103.pdf |archive-date=6 July 2003 |url-status=dead}}</ref> In 2004 Intel revealed plans for its next Itanium chipset, codenamed ''Bayshore'', to support [[PCI-e]] and [[DDR2 SDRAM|DDR2]] memory, but canceled it the same year.<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel |access-date=7 April 2022}}</ref><ref name="ibm_ditching_itanium"/>

==== Hewlett-Packard ====

Line 840:

Line 838:

=== Unix ===

* [[HP-UX]] 11 (~~supported~~ until ~~2025~~)

* [[HP-UX]] 11 (out of standard support; Mature Support on [[HPE Integrity]] through at least 2028<ref>{{Cite web |title=HP-UX support matrix |url=https://www.hpe.com/psnow/doc/4aa4-7673enw |quote=HPE Integrity: standard support through 31-Dec-20255 Mature Software Product Support without Sustaining Engineering through at least 31-Dec-2028}}</ref>)

=== BSD ===

* [[NetBSD]] (a tier II port<ref>{{Cite web|title=Platforms Supported by NetBSD|url=https://www.netbsd.org/ports/|access-date=~~2021~~-03-02|website=www.netbsd.org|archive-date=2021-02-27|archive-url=https://web.archive.org/web/20210227091416/http://www.netbsd.org/ports/|url-status=live}}</ref> ~~that~~ "is a work-in-progress effort to port NetBSD to the Itanium family of processors. Currently no formal release is available."<ref>{{Cite web|title=NetBSD/ia64|url=http://wiki.netbsd.org/ports/ia64/|access-date=2021-03-02|website=wiki.netbsd.org|archive-date=2018-04-27|archive-url=https://web.archive.org/web/20180427122809/http://wiki.netbsd.org/ports/ia64/|url-status=live}}</ref>)

* [[NetBSD]] (currently has no support;<ref>{{Cite web|title=Platforms Supported by NetBSD|url=https://www.netbsd.org/ports/|access-date=2025-12-31|website=www.netbsd.org|archive-date=2021-02-27|archive-url=https://web.archive.org/web/20210227091416/http://www.netbsd.org/ports/|url-status=live}}</ref> likely outdated page states "is a work-in-progress effort to port NetBSD to the Itanium family of processors. Currently no formal release is available."<ref>{{Cite web|title=NetBSD/ia64|url=http://wiki.netbsd.org/ports/ia64/|access-date=2021-03-02|website=wiki.netbsd.org|archive-date=2018-04-27|archive-url=https://web.archive.org/web/20180427122809/http://wiki.netbsd.org/ports/ia64/|url-status=live}}</ref>)

*[[FreeBSD]] (unsupported since 31 October 2018)

Line 849:

Line 847:

The Trillian Project was an effort by an industry consortium to port the [[Linux]] kernel to the Itanium processor. The project started in May 1999 with the goal of releasing the distribution in time for the initial release of Itanium, then scheduled for early 2000.<ref name="Sabbagh">{{cite web|last=Sabbagh|first=Dan|date=3 Feb 2000|title=Trillian releases Linux code for Itanium|url=http://www.vnunet.com/vnunet/news/2111194/trillian-releases-linux-code-itanium|archive-url=https://web.archive.org/web/20070930200218/http://www.vnunet.com/vnunet/news/2111194/trillian-releases-linux-code-itanium|archive-date=30 September 2007|url-status=dead|access-date=2007-03-20|work=vnunet.com}}</ref> By the end of 1999, the project included [[Caldera Systems]], [[CERN]], [[Cygnus Solutions]], [[Hewlett-Packard]], [[IBM]], [[Intel]], [[Red Hat]], [[Silicon Graphics|SGI]], [[SUSE S.A.|SuSE]], [[TurboLinux]] and [[VA Linux Systems]].<ref>{{cite press release|date=December 20, 1999|title=Leading Linux Distributors Join the Trillian Project|url=https://www.redhat.com/en/about/press-releases/press-trillian|access-date=2007-03-20|website=Red Hat}}</ref> The project released the resulting code in February 2000.<ref name="Sabbagh" /> The code then became part of the [[mainline Linux kernel]] more than a year before the release of the first Itanium processor. The Trillian project was able to do this for two reasons:

* the [[Free software|free]] and [[Open source software|open source]] [[GNU Compiler Collection|GCC]] compiler had already been enhanced to support the Itanium architecture.

* the [[Free software|free]] and [[Open source software|open source]] [[GNU Compiler Collection|GCC]] compiler had already been enhanced to support the Itanium architecture.<ref>{{Cite web |title=Did you know Origins were gonna have Merced? |url=https://forums.irixnet.org/thread-4714-post-34921.html#pid34921 |access-date=2025-11-11 |website=forums.irixnet.org}}</ref><ref>{{Cite web |title=GCC 4.2 Release Series — Changes, New Features, and Fixes - GNU Project |url=https://gcc.gnu.org/gcc-4.2/changes.html |access-date=2025-11-11 |website=gcc.gnu.org}}</ref>

* a free and open source simulator had been developed to simulate an Itanium processor on an existing computer.<ref>{{cite web| url = http://www.irisa.fr/caps/projects/ArchiCompil/iato/| title = IATO simulation environment}}</ref>

Line 855:

Line 853:

==== Distribution support ====

In 2005, Fedora Linux started adding support for Itanium<ref>{{Cite web|last=Shankland|first=Stephen|title=Fedora for Itanium taking baby steps|url=https://www.cnet.com/culture/fedora-for-itanium-taking-baby-steps/|access-date=2023-07-04|website=CNET|date=22 March 2005 |language=en}}</ref> and Novell added support for SUSE Linux.<ref>{{Cite web|last=Connor|first=Deni|date=2005-01-06|title=Novell releases SuSE Linux for HP Itanium servers|url=https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|access-date=2021-10-14|website=Network World|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029172431/https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|url-status=live}}</ref> In 2007, [[CentOS]] added support for Itanium in a new release.<ref>{{Cite web|title=CentOS 5 Linux released|url=https://www.itpro.co.uk/110119/centos-5-linux-released|access-date=2021-10-14|website=IT PRO|date=14 April 2007 |language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029170900/https://www.itpro.co.uk/110119/centos-5-linux-released|url-status=live}}</ref>

In 2003, Debian 3.0 (Woody) had support for Itanium<ref>{{cite web |last1=Debian |title=Release Notes for Debian GNU/Linux 3.0 (`woody'), IA-64 |url=https://www.debian.org/releases/woody/ia64/release-notes.en.txt |website=debian |publisher=Software in the Public Interest, Inc. |access-date=11 February 2026}}</ref>. In 2005, Fedora Linux started adding support for Itanium<ref>{{Cite web|last=Shankland|first=Stephen|title=Fedora for Itanium taking baby steps|url=https://www.cnet.com/culture/fedora-for-itanium-taking-baby-steps/|access-date=2023-07-04|website=CNET|date=22 March 2005 |language=en}}</ref> and Novell added support for SUSE Linux.<ref>{{Cite web|last=Connor|first=Deni|date=2005-01-06|title=Novell releases SuSE Linux for HP Itanium servers|url=https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|access-date=2021-10-14|website=Network World|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029172431/https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|url-status=live}}</ref> In 2007, [[CentOS]] added support for Itanium in a new release.<ref>{{Cite web|title=CentOS 5 Linux released|url=https://www.itpro.co.uk/110119/centos-5-linux-released|access-date=2021-10-14|website=IT PRO|date=14 April 2007 |language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029170900/https://www.itpro.co.uk/110119/centos-5-linux-released|url-status=live}}</ref>

* [[Debian]] (official support was dropped in Debian 8; unofficial support available through Debian Ports until June 2024<ref>{{cite web|title=Debian Ports|url=https://www.ports.debian.org|access-date=2024-10-27}}</ref>)

Line 866:

Line 864:

==== Deprecation ====

In 2009, Red Hat dropped Itanium support in Enterprise Linux 6.<ref name="red-hat-to-drop-itanium">{{Cite web|last=Ricknäs|first=Mikael|date=2009-12-21|title=Red Hat to drop Itanium support in Enterprise Linux 6|url=https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|access-date=2021-10-14|website=[[Computerworld]]|language=en|archive-date=2021-10-28|archive-url=https://web.archive.org/web/20211028172143/https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|url-status=live}}</ref> Ubuntu 10.10 dropped support for Itanium.<ref>{{Cite web|last=Clark|first=Jack|title=SPARC and Itanium support discontinued in Ubuntu 10.10|url=https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|access-date=2021-10-14|website=ZDNet|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029180056/https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|url-status=live}}</ref> In 2021, Linus Torvalds marked the Itanium code as orphaned. Torvalds said:

In 2009, Red Hat dropped Itanium support in Enterprise Linux 6.<ref name="red-hat-to-drop-itanium">{{Cite web|last=Ricknäs|first=Mikael|date=2009-12-21|title=Red Hat to drop Itanium support in Enterprise Linux 6|url=https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|access-date=2021-10-14|website=[[Computerworld]]|language=en|archive-date=2021-10-28|archive-url=https://web.archive.org/web/20211028172143/https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|url-status=live}}</ref> Ubuntu 10.10 dropped support for Itanium.<ref>{{Cite web|last=Clark|first=Jack|title=SPARC and Itanium support discontinued in Ubuntu 10.10|url=https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|access-date=2021-10-14|website=ZDNet|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029180056/https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|url-status=live}}</ref> In 2021, Linus Torvalds marked the Itanium code as orphaned. Torvalds said: "HPE no longer accepts orders for new Itanium hardware, and Intel stopped accepting orders a year ago. While intel{{Sic}} is still officially shipping chips until July 29, 2021, it's unlikely that any such orders actually exist. [[He's dead, Jim|It's dead, Jim]]."<ref>{{Cite news|first=Tim|last=Anderson|title='It's dead, Jim': Torvalds marks Intel Itanium processors as orphaned in Linux kernel|url=https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|access-date=2021-10-14|work=[[The Register]]|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029174912/https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|url-status=live}}</ref><ref>{{Cite web|title=kernel/git/torvalds/linux.git - Linux kernel source tree|url=https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|access-date=2021-10-14|website=[[kernel.org]]|archive-date=2021-11-03|archive-url=https://web.archive.org/web/20211103183816/https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|url-status=live}}</ref>

"HPE no longer accepts orders for new Itanium hardware, and Intel stopped accepting orders a year ago. While intel is still officially shipping chips until July 29, 2021, it's unlikely that any such orders actually exist. [[He's dead, Jim|It's dead, Jim]]."<ref>{{Cite news|first=Tim|last=Anderson|title='It's dead, Jim': Torvalds marks Intel Itanium processors as orphaned in Linux kernel|url=https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|access-date=2021-10-14|work=[[The Register]]|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029174912/https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|url-status=live}}</ref><ref>{{Cite web|title=kernel/git/torvalds/linux.git - Linux kernel source tree|url=https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|access-date=2021-10-14|website=[[kernel.org]]|archive-date=2021-11-03|archive-url=https://web.archive.org/web/20211103183816/https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|url-status=live}}</ref>

Support for Itanium was removed in Linux 6.7<ref>{{Cite web |title=kernel/git/next/linux-next.git - The linux-next integration testing tree |url=https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=cf8e8658100d4eae80ce9b21f7a81cb024dd5057 |access-date=2023-09-18 |website=git.kernel.org}}</ref><ref>{{Cite web |title=Linux 6.7 Set To Drop Support For Itanium IA-64 |url=https://www.phoronix.com/news/Linux-6.7-To-Drop-Itanium-IA-64 |access-date=2023-09-18 |website=www.phoronix.com |language=en}}</ref> and is since then maintained [[wiktionary:out-of-tree|out-of-tree]].<ref>{{cite web |url=https://github.com/linux-ia64/ |title=linux-ia64 |website=GitHub |quote=Maintenance and development of the Linux operating system for Intel Itanium architecture (IA-64) |access-date=October 1, 2024}}</ref><ref>{{cite web |url=http://epic-linux.org/ |title=EPIC Linux |access-date=October 1, 2024}}</ref>

Line 893:

Line 889:

=== NonStop OS ===

[[NonStop OS]] was ported from [[MIPS architecture|MIPS]]-based hardware to Itanium in 2005.<ref>{{cite web|url=https://www.hpe.com/psnow/doc/4AA0-6149ENW|title=HPE NonStop OS|date=April 2018|publisher=HPE|access-date=2021-11-22|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122135935/https://www.hpe.com/psnow/doc/4AA0-6149ENW|url-status=live}}</ref> NonStop OS was later ported to x86-64 in 2015. Sales of Itanium-based NonStop hardware ended in 2020, with support ending in 2025.<ref name="hpe-brochure">{{cite web|url=https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|title=HPE NonStop family of systems|publisher=HPE|date=May 2021|access-date=2021-11-22|archive-date=2022-01-21|archive-url=https://web.archive.org/web/20220121201745/https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|url-status=live}}</ref><ref>{{cite web|url=https://connect2nonstop.com/2371-2/|title=News from HPE's NonStop Enterprise Division|author=Prashanth Kamath U|date=2019-07-30|access-date=2021-11-22|website=The Connection|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122140545/https://connect2nonstop.com/2371-2/|url-status=live}}</ref>

[[NonStop OS|Tandem NonStop OS]] was ported from [[MIPS architecture|MIPS]]-based hardware to Itanium in 2005.<ref>{{cite web|url=https://www.hpe.com/psnow/doc/4AA0-6149ENW|title=HPE NonStop OS|date=April 2018|publisher=HPE|access-date=2021-11-22|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122135935/https://www.hpe.com/psnow/doc/4AA0-6149ENW|url-status=live}}</ref> NonStop OS was later ported to x86-64 in 2015. Sales of Itanium-based NonStop hardware ended in 2020, with support ending in 2025.<ref name="hpe-brochure">{{cite web|url=https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|title=HPE NonStop family of systems|publisher=HPE|date=May 2021|access-date=2021-11-22|archive-date=2022-01-21|archive-url=https://web.archive.org/web/20220121201745/https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|url-status=live}}</ref><ref>{{cite web|url=https://connect2nonstop.com/2371-2/|title=News from HPE's NonStop Enterprise Division|author=Prashanth Kamath U|date=2019-07-30|access-date=2021-11-22|website=The Connection|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122140545/https://connect2nonstop.com/2371-2/|url-status=live}}</ref>

=== Compiler ===

[[GNU Compiler Collection]] deprecated support for IA-64 in GCC 10, after Intel announced the planned phase-out of this ISA.<ref>{{cite web |title=Intel Itanium IA-64 Support To Be Deprecated By GCC 10, Planned Removal In GCC 11 |url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-IA-64-GCC-Deprecation |website=Phoronix |access-date=2020-07-09 |archive-date=2020-07-11 |archive-url=https://web.archive.org/web/20200711001829/https://www.phoronix.com/scan.php?page=news_item&px=Intel-IA-64-GCC-Deprecation |url-status=live }}</ref> [[LLVM]] (Clang) dropped Itanium support in version 2.6.<ref>{{Cite web|date=Jul 24, 2009|title=Remove the IA-64 backend. · llvm/llvm-project@1715115 · GitHub|url=https://github.com/llvm/llvm-project/commit/17151155ed8f83dcbb5db69bca2839ac2da19e0e|website=GitHub}}</ref>

However, Itanium's C++ ABI continues to be the ABI used for both GCC and LLVM on most CPU architectures.<ref>{{Cite web |title=ABI Policy and Guidelines |url=https://gcc.gnu.org/onlinedocs/libstdc++/manual/abi.html |access-date=2025-11-11 |website=gcc.gnu.org}}</ref>

=== Virtualization and emulation ===

Line 1,042:

Line 1,040:

| access-date=November 25, 2022

}}</ref>

Itanium failed to make significant inroads against [[IA-32]] or RISC, and suffered further following the arrival of [[x86-64]] systems which offered ~~greater~~ compatibility with older x86 applications.

Itanium failed to make significant inroads against [[IA-32]] or RISC, and suffered further following the arrival of [[x86-64]] systems which offered complete compatibility with older x86 applications at full, native performance without emulation.

In a 2009 article on the history of the processor — "How the Itanium Killed the Computer Industry" — journalist [[John C. Dvorak]] reported "This continues to be one of the great fiascos of the last 50 years".<ref>{{cite web

Line 1,158:

Line 1,156:

Line 1,167:

Line 1,165:

[[Category:VLIW microprocessors]]

[[Category:Products and services discontinued in 2021]]

[[Category:HP microprocessors]]

@@ Line 5: / Line 5: @@
   | image=Intel Itanium logo.svg
   | image_size = 150px
-  | caption=
+  | caption=Logo from 2006 to 2009
   | produced-start={{start date and age|2001|06}}{{Efn|Itanium was launched on 29 May,<ref>{{cite web |title=Intel officially launches 64-bit Itanium chip |url=https://www.computerworld.com/article/2582076/intel-officially-launches-64-bit-itanium-chip.html |website=[[Computerworld]] |date=29 May 2001}}</ref><ref>{{cite web |last1=Fordahl |first1=Matthew |title=Intel, HP Launch New Processor |url=https://abcnews.go.com/Technology/story?id=98536&page=1 |website=[[ABC News (United States)|ABC News]] |date=30 May 2001}}</ref><ref>{{cite web |last1=Bekker |first1=Scott |title=Intel Launches Itanium: OEMs Unveil Systems |url=https://rcpmag.com/articles/2001/05/29/intel-launches-itanium-oems-unveil-systems.aspx |website=RCP Mag |date=29 May 2001}}</ref><ref>{{cite web |last1=Kerridge |first1=Suzanna |title=Intel opens up about forthcoming Itanium family |url=https://www.zdnet.com/article/intel-opens-up-about-forthcoming-itanium-family/ |website=[[ZDNet]] |date=18 May 2001}}</ref> but the computers containing it shipped to customers in June.}}
   | produced-end={{end date and age|2020|01|30}}<ref name="theend">{{cite web|url=https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf|title=Select Intel Itanium Processors and Intel Scalable Memory Buffer, PCN 116733-00, Product Discontinuance, End of Life|date=January 30, 2019|publisher=Intel|access-date=May 20, 2020|archive-date=May 22, 2020|archive-url=https://web.archive.org/web/20200522180927/https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf|url-status=live}}<br />(January 30, 2020 was the last date for placing an order, all shipped no later than July 29, 2021).</ref>
@@ Line 24: / Line 24: @@
   | l3cache=Up to 32 MB
   | soldby=[[Intel]]
-  | designfirm=Intel<br/>Hewlett-Packard
+  | designfirm=Intel<br/>[[Hewlett-Packard]]
-|model1=Itanium|model2=Itanium 2|model3=Itanium 9000 series|core1=Merced|core2=McKinley|core3=Madison 3M/6M/9M|core4=Deerfield (Madison LV)|core5=Hondo{{efn|Hondo is an HP product, not an Intel product}}|core6=Fanwood (Madison DP)|core7=Montecito|core8=Montvale|core9=Tukwila|core10=Poulson|qpi-slowest=4.8|qpi-fastest=6.4|sock1=[[PAC 418]]|sock2=[[PAC 611]]|sock3=[[LGA 1248]]|model4=Itanium 9100 series|model5=Itanium 9300 series|model6=Itanium 9500 series|model7=Itanium 9700 series|l1cache=Up to 32 KB per core (data)<br/> Up to 32 KB per core (instructions)|l4cache=32 MB (Hondo only)|application=High-end/[[Mission critical|mission critical servers]]<br/>[[High performance computing]]<br/>High-end workstations|data-width=64 bits|address-width=64 bits|virtual-width=64 bits|microarch=P7|core11=Kittison|extensions1=[[SpeedStep|EIST]], [[VT-x]], [[VT-d]], [[VT-i]]|pack1=Pin Array Cartridge (PAC)|pack2=[[Flip-chip]] [[land grid array]] (FC-LGA)|support_status=Unsupported|amountmemory=Up to 1.5 TB|memory1=Up to [[DDR3 SDRAM|DDR3]] with [[Error correction code|ECC]] support}}
+|model1=Itanium|model2=Itanium 2|model3=Itanium 9000 series|core1=Merced|core2=McKinley|core3=Madison 3M/6M/9M|core4=Deerfield (Madison LV)|core5=Hondo{{efn|Hondo is an HP product, not an Intel product}}|core6=Fanwood (Madison DP)|core7=Montecito|core8=Montvale|core9=Tukwila|core10=Poulson|qpi-slowest=4.8|qpi-fastest=6.4|sock1=[[PAC 418]]|sock2=[[PAC 611]]|sock3=[[LGA 1248]]|model4=Itanium 9100 series|model5=Itanium 9300 series|model6=Itanium 9500 series|model7=Itanium 9700 series|l1cache=Up to 32 KB per core (data)<br/> Up to 32 KB per core (instructions)|l4cache=32 MB (Hondo only)|application=High-end/[[Mission critical|mission critical servers]]<br/>[[High performance computing]]<br/>High-end workstations|data-width=64 bits|address-width=64 bits|virtual-width=64 bits|microarch=P7|core11=Kittson|extensions1=[[SpeedStep|EIST]], [[VT-x]], [[VT-d]], [[VT-i]]|pack1=Pin Array Cartridge (PAC)|pack2=[[Flip-chip]] [[land grid array]] (FC-LGA)|support_status=Unsupported|amountmemory=Up to 1.5 TB|memory1=Up to [[DDR3 SDRAM|DDR3]] with [[Error correction code|ECC]] support}}
-'''Itanium''' ({{IPAc-en|aɪ|ˈ|t|eɪ|n|i|ə|m}}; {{respell|eye|TAY|nee-əm}}) is a discontinued family of [[64-bit computing|64-bit]] [[Intel]] [[microprocessor]]s that implement the [[Intel Itanium architecture]] (formerly called IA-64). The Itanium architecture originated at [[Hewlett-Packard]] (HP), and was later jointly developed by HP and Intel. Launching in June 2001, Intel initially marketed the processors for [[enterprise server]]s and [[high-performance computing]] systems. In the concept phase, engineers said "we could run circles around PowerPC...we could kill the x86". Early predictions were that IA-64 would expand to the lower-end servers, supplanting [[Xeon]], and eventually penetrate into the [[personal computer]]s, eventually to supplant [[Reduced instruction set computer|reduced instruction set computing]] (RISC) and [[complex instruction set computing]] (CISC) architectures for all general-purpose applications.
+'''Itanium''' ({{IPAc-en|aɪ|ˈ|t|eɪ|n|i|ə|m}}; {{respell|eye|TAY|nee-əm}}) is a discontinued family of [[64-bit computing|64-bit]] [[Intel]] [[microprocessor]]s that implement the [[Intel Itanium architecture]] (formerly called IA-64). The Itanium architecture originated at [[Hewlett-Packard]] (HP), and was later jointly developed by HP and Intel. Launching in June 2001, Intel initially marketed the processors for [[enterprise server]]s and [[high-performance computing]] systems. In the concept phase, engineers said "we could run circles around [[PowerPC]]...we could kill the x86". Early predictions were that IA-64 would expand to the lower-end servers, supplanting [[Xeon]], and eventually penetrate into the [[personal computer]]s, eventually to supplant [[Reduced instruction set computer|reduced instruction set computing]] (RISC) and [[complex instruction set computing]] (CISC) architectures for all general-purpose applications.
-When first released in 2001 after a decade of development, Itanium's performance was disappointing compared to better-established RISC and CISC processors. Emulation to run existing x86 applications and operating systems was particularly poor. Itanium-based systems were produced by HP and its successor [[Hewlett Packard Enterprise]] (HPE) as the [[HPE Integrity Servers|Integrity Servers]] line, and by several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for [[Enterprise information system|enterprise-class systems]], behind [[x86-64]], [[Power ISA]], and [[SPARC]].<ref name="ITJungle">{{cite web
+When first released in 2001 after a decade of development, Itanium's performance was disappointing compared to better-established [[RISC]] and [[Complex instruction set computer|CISC]] processors. Emulation to run existing x86 applications and operating systems was particularly poor. Itanium-based systems were produced by HP and its successor [[Hewlett Packard Enterprise]] (HPE) as the [[HPE Integrity Servers|Integrity Servers]] line, and by several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for [[Enterprise information system|enterprise-class systems]], behind [[x86-64]], [[Power ISA]], and [[SPARC]].<ref name="ITJungle">{{cite web
   |url          = http://www.itjungle.com/tlb/tlb052708-story03.html
   |title        = The Server Biz Enjoys the X64 Upgrade Cycle in Q1
@@ Line 41: / Line 41: @@
   |work         = IT Jungle
   |df           = mdy-all
-}}</ref>{{Update inline|reason=That's 9 years old, although it's probably still true, unless it's now behind z/Architecture as well.|date=April 2017}}
+}}</ref>
 In February 2017, Intel released the final generation, Kittson, to test customers, and in May began shipping in volume.<ref name="Davis 2017">{{cite web
@@ Line 85: / Line 85: @@
   }}</ref> In 1993 HP held an internal competition to design the best (simulated) microarchitectures of a RISC and an EPIC type, led by Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] respectively. The EPIC team won, with over double the simulated performance of the RISC competitor.<ref name="nyt_merced">{{cite web |last1=Markoff |first1=John |title=Inside Intel, The Future is Riding on the Merced Chip |url=https://archive.org/details/TheJerusalemPost1998IsraelEnglish/Apr%2006%201998%2C%20The%20Jerusalem%20Post%2C%20%2319898%2C%20Israel%20%28en%29/page/n12/mode/1up |publisher=[[The New York Times]], republised by [[The Jerusalem Post]] |date=5 April 1998}}</ref>
-At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>
+At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium, too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>
 In November 1993 HP approached Intel, seeking collaboration on an innovative future architecture.<ref name="countdown">{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}}</ref>{{refn|{{cite web |last1=Alpert |first1=Donald |title=Intel Itanium Processor (Merced) |url=https://camelback-comparch.com/about/technical-highlights/#merced |date=July 2003}} Alpert was the chief architect of the original P7 and the top engineering manager of Merced<ref>{{cite web |last1=Smotherman |first1=Mark |title=Who are the Computer Architects? |url=https://people.computing.clemson.edu/~mark/architects.html |publisher=[[Clemson University]] }} See the sections "Independence architecture" and "Wintel".</ref>}} At the time Intel was looking to extend x86 to 64 bits in a processor codenamed P7, which they found challenging.<ref>{{cite web |last1=DeMone |first1=Paul |title=What's Up With Willamette? (Part 1) |url=https://www.realworldtech.com/willamette-basics/ |website=Real World Tech |date=3 March 2000}}</ref> Later Intel claimed that four different design teams had explored 64-bit extensions, but each of them concluded that it was not economically feasible.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel takes slow road to 64-bit PC chips |url=https://www.cnet.com/tech/tech-industry/intel-takes-slow-road-to-64-bit-pc-chips/ |website=[[CNET]] |date=21 February 2003}}</ref> At the meeting with HP, Intel's engineers were impressed when Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] presented the PA-WideWord architecture they had designed to replace [[PA-RISC]]. "When we saw WideWord, we saw a lot of things we had only been looking at doing, already in their full glory", said Intel's [[John Crawford (engineer)|John Crawford]], who in 1994 became the chief architect of Merced, and who had earlier argued against extending the x86 with P7. HP's Gupta recalled: "I looked Albert Yu [Intel's general manager for microprocessors] in the eyes and showed him we could run circles around [[PowerPC]], that we could kill PowerPC, that we could kill the x86."<ref name="gambles"/> Soon Intel and HP started conducting in-depth technical discussions at an HP office, where each side had six{{Refn|<ref name="countdown"/><ref name="birth">{{cite web |last1=Britt |first1=Russ |title=The birth of a new processor |url=https://www.edn.com/the-birth-of-a-new-processor/ |website=[[EDN (magazine)|EDN]] |date=1 January 2000}}</ref> (The {{Define|ACM|architecture, compilers, microarchitecture}} committee with 5 people from each side<ref>{{cite web |last1=Smotherman |first1=Mark |title=Historical background for EPIC instruction set architectures |url=https://people.computing.clemson.edu/~mark/epic.html |publisher=[[Clemson University]] |access-date=3 June 2022}}</ref> was probably a different entity.)}} engineers who exchanged and discussed both companies' confidential architectural research. They then decided to use not only PA-WideWord, but also the more experimental [[HP Labs]] PlayDoh as the source of their joint future architecture.<ref name="simplicity">{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/ |website=Real World Tech |date=27 October 1999}}</ref><ref>{{cite web |last1=Kathail |first1=Vinod |last2=Schlansker |first2=Michael S. |last3=Rau |first3=B. Ramakrishna |title=HPL-PD Architecture Specification: Version 1.1 |url=https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |publisher=[[HP Labs|HP Laboratories]] |access-date=2023-07-05 |archive-date=2024-02-04 |archive-url=https://web.archive.org/web/20240204063521/https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |url-status=dead }}</ref> Convinced of the superiority of the new project, in 1994 Intel canceled their existing plans for P7.
@@ Line 136: / Line 136: @@
   | archive-date=May 3, 2012
   | archive-url=https://web.archive.org/web/20120503094946/http://www.anandtech.com/show/1854
-  | url-status=live
+  | url-status=dead
   }}</ref><ref name="Venturebeat">{{cite web
   | url=https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/
@@ Line 160: / Line 160: @@
   }}</ref>
-Several groups ported operating systems for the architecture, including [[Microsoft Windows]], [[OpenVMS]], [[Linux]], [[HP-UX]], [[Solaris (operating system)|Solaris]],<ref name="Solaris-Merced1">{{cite web
+Several groups ported operating systems for the architecture, including [[Microsoft Windows]], [[OpenVMS]], [[Linux]], [[HP-UX]], [[Oracle Solaris|Solaris]],<ref name="Solaris-Merced1">{{cite web
   | url=http://www.computerworld.com/home/news.nsf/all/9909013sunsol
   | title=Solaris for IA-64 coming this fall
@@ Line 199: / Line 199: @@
   | date=October 4, 1999
   | website=[[CNET]]
-  }}</ref>
+  }}</ref> Within hours, the name '''''Itanic''''' had been coined on a [[Usenet]] newsgroup, a reference to the [[RMS Titanic|RMS ''Titanic'']], the "unsinkable" [[ocean liner]] that sank on her maiden voyage in 1912.<ref>{{cite newsgroup
-Within hours, the name '''''Itanic''''' had been coined on a [[Usenet]] newsgroup, a reference to the [[RMS Titanic|RMS ''Titanic'']], the "unsinkable" [[ocean liner]] that sank on her maiden voyage in 1912.<ref>{{cite newsgroup
   | url=https://groups.google.com/d/msg/comp.sys.mac.advocacy/UiOOaXF3-lI/f3nje9CHPx0J
   | title=Re:Itanium
@@ Line 274: / Line 273: @@
   | archive-url=https://web.archive.org/web/20191217201629/https://www.eetimes.com/itanium-era-dawns/
   | url-status=live
-  }}</ref>
+  }}</ref> Itanium competed at the low-end (primarily four-[[central processing unit|CPU]] and smaller systems) with servers based on [[x86]] processors, and at the high-end with [[IBM Power microprocessors|IBM POWER]] and [[Sun Microsystems]] [[SPARC]] processors. Intel repositioned Itanium to focus on the high-end business and [[High-performance computing|HPC]] computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the [[PA-RISC]] in HP systems, [[DEC Alpha|Alpha]] in Compaq systems and [[MIPS architecture|MIPS]] in [[Silicon Graphics|SGI]] systems, though IBM also delivered a supercomputer based on this processor.<ref name="Thunder">{{cite web
-Itanium competed at the low-end (primarily four-[[central processing unit|CPU]] and smaller systems) with servers based on [[x86]] processors, and at the high-end with [[IBM Power microprocessors|IBM POWER]] and [[Sun Microsystems]] [[SPARC]] processors. Intel repositioned Itanium to focus on the high-end business and [[High-performance computing|HPC]] computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the [[PA-RISC]] in HP systems, [[DEC Alpha|Alpha]] in Compaq systems and [[MIPS architecture|MIPS]] in [[Silicon Graphics|SGI]] systems, though IBM also delivered a supercomputer based on this processor.<ref name="Thunder">{{cite web
   | url=http://www.top500.org/system/ranking/5597
   | title=Titan Cluster Itanium 800&nbsp;MHz
@@ Line 293: / Line 291: @@
   | date=December 11, 2001
   | access-date=July 4, 2023
-  }}</ref> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium&nbsp;2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.
+  }}</ref> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium&nbsp;2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.{{clarify|reason=confusingly written sentence|date=December 2025}}
 === Itanium 2 (McKinley and Madison): 2002–2006 ===
@@ Line 337: / Line 335: @@
 The '''Itanium 2''' processor was released in July 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium&nbsp;2, code-named ''McKinley'', was jointly developed by HP and Intel, led by the HP team at [[Fort Collins, Colorado]], [[tape-out|taping out]] in December 2000. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem by approximately halving the latency and doubling the fill bandwidth of each of the three levels of cache, while expanding the L2 cache from 96 to 256 KB. Floating-point data is excluded from the L1 cache, because the L2 cache's higher bandwidth is more beneficial to typical floating-point applications than low latency. The L3 cache is now integrated on-chip rather than on a separate die, tripling in associativity and doubling in bus width.  McKinley also greatly increases the number of possible instruction combinations in a VLIW-bundle and reaches 25% higher frequency, despite having only eight pipeline stages versus Merced's ten.<ref>{{cite web |last1=Hammond |first1=Gary |last2=Naffziger |first2=Sam |title=Next Generation Itanium™ Processor Overview |url=http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-url=https://web.archive.org/web/20030706123550/http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-date=6 July 2003 |url-status=dead}}</ref><ref name="HP_McKinley_wp"/>
-''McKinley'' contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5&nbsp;mm by 21.6&nbsp;mm (421&nbsp;mm<sup>2</sup>) and was fabricated in a 180&nbsp;nm, bulk CMOS process with six layers of aluminium metallization.<ref>{{cite journal |last1=Naffzinger |first1=Samuel D. |first2=Glenn T. |last2=Colon-Bonet |first3=Timothy |last3=Fischer |first4=Reid |last4=Riedlinger |first5=Thomas J. |last5=Sullivan |first6=Tom |last6=Grutkowski |date=November 2002 |title=The implementation of the Itanium&nbsp;2 microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=37 |issue=11 |pages=1448–1460 |doi=10.1109/JSSC.2002.803943 |bibcode=2002IJSSC..37.1448N |url=http://cpus.hp.com/technical_references/jssc_naffziger.pdf|archive-url=https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf |archive-date=2003-03-22 |url-status=dead}}</ref><ref>{{cite web |last1=Soltis |first1=Don |last2=Gibson |first2=Mark |title=Itanium® 2 Processor Microarchitecture Overview |url=http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |website=[[Hot Chips]] |archive-url=https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |archive-date=31 May 2005 |url-status=dead}}</ref><ref>{{cite web |last1=Naffziger |first1=Samuel |last2=Hammond |first2=Gary |title=The Implementation of the Next-Generation 64b Itanium Microprocessor |url=http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-url=https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-date=29 October 2004 |url-status=dead}}</ref> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency to 800&nbsp;MHz.<ref>{{cite web |last1=Krazit |first1=Tom |title=Intel details Itanium 2 bug |url=https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html |website=[[Computerworld]] |date=12 May 2003 |access-date=30 March 2022}}</ref>
+''McKinley'' contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5&nbsp;mm by 21.6&nbsp;mm (421&nbsp;mm<sup>2</sup>) and was fabricated in a 180&nbsp;nm, bulk CMOS process with six layers of aluminium metallization.<ref>{{cite journal |last1=Naffzinger |first1=Samuel D. |first2=Glenn T. |last2=Colon-Bonet |first3=Timothy |last3=Fischer |first4=Reid |last4=Riedlinger |first5=Thomas J. |last5=Sullivan |first6=Tom |last6=Grutkowski |date=November 2002 |title=The implementation of the Itanium&nbsp;2 microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=37 |issue=11 |pages=1448–1460 |doi=10.1109/JSSC.2002.803943 |bibcode=2002IJSSC..37.1448N |url=http://cpus.hp.com/technical_references/jssc_naffziger.pdf|archive-url=https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf |archive-date=2003-03-22 |url-status=dead}}</ref><ref>{{cite web |last1=Soltis |first1=Don |last2=Gibson |first2=Mark |title=Itanium® 2 Processor Microarchitecture Overview |url=http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |website=[[Hot Chips]] |archive-url=https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |archive-date=31 May 2005 |url-status=dead}}</ref><ref>{{cite web |last1=Naffziger |first1=Samuel |last2=Hammond |first2=Gary |title=The Implementation of the Next-Generation 64b Itanium Microprocessor |url=http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-url=https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-date=29 October 2004 |url-status=dead}}</ref> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency from the original 1&nbsp;GHz to 800&nbsp;MHz.<ref>{{cite web |last1=Krazit |first1=Tom |title=Intel details Itanium 2 bug |url=https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html |website=[[Computerworld]] |date=12 May 2003 |access-date=30 March 2022}}</ref>
-In 2003, [[Advanced Micro Devices|AMD]] released the [[Opteron]] CPU, which implements its own [[64-bit computing|64-bit]] architecture called [[AMD64]]. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from [[x86]]. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 [[instruction set architecture]] instead of IA-64 in its [[Xeon]] microprocessors in 2004, resulting in a new industry-wide ''de facto'' standard.<ref name="cautionary"/>
+In 2003, [[AMD]] released the [[Opteron]] CPU, which implements its own [[64-bit computing|64-bit]] architecture called [[X86-64#AMD64|AMD64]]. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from [[x86]]. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 [[instruction set architecture]] (instead of IA-64) in its [[Xeon]] microprocessors in 2004, resulting in a new industry-wide ''de facto'' standard.<ref name="cautionary"/>
 In 2003, Intel released a new Itanium&nbsp;2 family member, codenamed ''Madison'', initially with up to 1.5&nbsp;GHz frequency and 6 MB of L3 cache. The ''Madison 9M'' chip released in November 2004 had 9 MB of L3 cache and frequency up to 1.6&nbsp;GHz, reaching 1.67&nbsp;GHz in July 2005. Both chips used a 130&nbsp;nm process and were the basis of all new Itanium processors until Montecito was released in July 2006, specifically ''Deerfield'' being a low wattage ''Madison'', and ''Fanwood'' being a version of ''Madison 9M'' for lower-end servers with one or two CPU sockets.
@@ Line 406: / Line 404: @@
 }}
 {{Main|Montecito (processor)}}
-In early 2003, due to the success of IBM's dual-core [[POWER4]], Intel announced that the first [[90 nm]] Itanium processor, codenamed ''Montecito'', would be delayed to 2005 so as to change it into a dual-core, thus merging it with the ''Chivano'' project.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel accelerates Itanium schedule |url=https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref name="qa">{{cite news |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel's summer of servers |url=https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/ |website=[[The Globe and Mail]] |date=9 July 2003 |access-date=27 April 2022}}</ref> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of [[hyper-threading]] increases Montecito's performance by 10-20% and that its frequency could reach 2&nbsp;GHz.<ref name="monty">{{cite web |last1=Kanellos |first1=Michael |title=Intel fills in more details on Itanium family |url=https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref>{{cite web |last1=Wilson |first1=Derek |title=Intel Developer Forum Fall 2004: Day 1 Keynote |url=https://www.anandtech.com/show/1465/3 |website=[[AnandTech]] |access-date=28 April 2022}}</ref> After a delay to "mid-2006" and reduction of the frequency to 1.6&nbsp;GHz,<ref>{{cite news |last1=Shankland |first1=Stephen |title=Intel pushes back Itanium chips, revamps Xeon |url=https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/ |website=[[CNET]] |access-date=3 April 2022}}</ref> on July 18 Intel delivered ''Montecito'' (marketed as the '''Itanium&nbsp;2 9000''' series), a [[multi-core processor|dual-core]] processor with a [[Multithreading (computer architecture)#Coarse-grained multithreading|switch-on-event multithreading]] and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<ref name="CW1">{{cite web
+In early 2003, due to the success of IBM's dual-core [[POWER4]], Intel announced that the first [[90 nm]] Itanium processor, codenamed ''Montecito'', would be delayed to 2005 so as to change it into a dual-core, thus merging it with the ''Chivano'' project.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel accelerates Itanium schedule |url=https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref name="qa">{{cite news |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel's summer of servers |url=https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/ |website=[[The Globe and Mail]] |date=9 July 2003 |access-date=27 April 2022}}</ref> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of [[hyper-threading]] increases Montecito's performance by 10-20% and that its frequency could reach 2&nbsp;GHz.<ref name="monty">{{cite web |last1=Kanellos |first1=Michael |title=Intel fills in more details on Itanium family |url=https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref>{{cite web |last1=Wilson |first1=Derek |title=Intel Developer Forum Fall 2004: Day 1 Keynote |url=https://www.anandtech.com/show/1465/3 |archive-url=https://web.archive.org/web/20210917112245/https://www.anandtech.com/show/1465/3 |url-status=dead |archive-date=September 17, 2021 |website=[[AnandTech]] |access-date=28 April 2022}}</ref> After a delay to "mid-2006" and reduction of the frequency to 1.6&nbsp;GHz,<ref>{{cite news |last1=Shankland |first1=Stephen |title=Intel pushes back Itanium chips, revamps Xeon |url=https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/ |website=[[CNET]] |access-date=3 April 2022}}</ref> on July 18 Intel delivered ''Montecito'' (marketed as the '''Itanium&nbsp;2 9000''' series), a [[multi-core processor|dual-core]] processor with a [[Multithreading (computer architecture)#Coarse-grained multithreading|switch-on-event multithreading]] and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<ref name="CW1">{{cite web
   |url          = https://www.computerworld.com/article/2536018/-tukwila--itanium-servers-due-early-next-year--intel-says.html
   |title        = 'Tukwila' Itanium servers due early next year, Intel says
@@ Line 467: / Line 466: @@
   | name=9500 and 9700 series
   | produced-start=8 November 2012
-  | produced-end=30 January 2020<ref>{{cite web |last1=Shilov |first1=Anton |title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums |url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |website=[[AnandTech]] |access-date=28 April 2022}}</ref>
+  | produced-end=30 January 2020<ref>{{cite web |last1=Shilov |first1=Anton |title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums |url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |archive-url=https://web.archive.org/web/20190201050122/https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |url-status=dead |archive-date=February 1, 2019 |website=[[AnandTech]] |access-date=28 April 2022}}</ref>
   | slowest=1.73
   | fastest=2.67
@@ Line 503: / Line 502: @@
 [[File:Intel Itanium 9300 with cap removed.jpg|thumb|Intel Itanium 9300 with cap removed]]
 {{Main|Tukwila (processor)|}}
 The original code name for the first Itanium with more than two cores was Tanglewood, but it was changed to Tukwila in late 2003 due to trademark issues.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel changes code name of future Itanium |url=https://www.cnet.com/tech/tech-industry/intel-changes-code-name-of-future-itanium/ |website=[[CNET]] |access-date=4 July 2023}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Trademark flap prompts Intel to rename Tanglewood |url=https://www.infoworld.com/article/2678103/trademark-flap-prompts-intel-to-rename-tanglewood.html |website=[[InfoWorld]] |date=18 December 2003 |access-date=31 March 2022}}</ref> Intel discussed a "middle-of-the-decade Itanium" to succeed Montecito, achieving ten times the performance of Madison.<ref>{{cite news |last1=Vance |first1=Ashlee |author-link=Ashlee Vance |title=Tanglewood to run 10x faster than Madison |url=https://www.theregister.com/2003/05/01/tanglewood_to_run_10x_faster1/ |work=[[The Register]] |access-date=27 April 2022}}</ref><ref name="qa"/> It was being designed by the famed [[DEC Alpha]] team and was expected have eight new multithreading-focused cores. Intel claimed "a lot more than two" cores and more than seven times the performance of Madison.<ref>{{cite web |last1=McMillan |first1=Robert |title=FALL IDF: Intel readies 8-core, 16-core Itanium 2 |url=https://www.infoworld.com/article/2676169/fall-idf--intel-readies-8-core--16-core-itanium-2.html |website=[[InfoWorld]] |date=17 September 2003 |access-date=31 March 2022}}</ref><ref>{{cite web |last1=Shankland |first1=Stephen |title='Tanglewood' to top Intel chip show |url=https://www.cnet.com/tech/tech-industry/tanglewood-to-top-intel-chip-show/ |website=[[CNET]] |access-date=31 March 2022}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Itanium 2 Montecito to be multithreaded |url=https://www.computerweekly.com/news/2240053525/Itanium-2-Montecito-to-be-multithreaded |website=[[Computer Weekly]] |access-date=31 March 2022}}</ref> In early 2004 Intel told of "plans to achieve up to double the performance over the Intel Xeon processor family at platform cost parity by 2007".<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel}}</ref> By early 2005 Tukwila was redefined, now having fewer cores but focusing on single-threaded performance and multiprocessor scalability.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel to spotlight new Itanium: 'Poulson' |url=https://www.cnet.com/tech/tech-industry/intel-to-spotlight-new-itanium-poulson/ |website=[[CNET]] |access-date=31 March 2022}}</ref>
@@ Line 589: / Line 589: @@
   |archive-url         = https://web.archive.org/web/20171201034615/http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf
   |url-status  = dead
-  }}</ref>
+  }}</ref> Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<ref>{{cite web
-Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<ref>{{cite web
   | url=https://www.realworldtech.com/poulson-preview/
   | title=New Itanium Microarchitecture at ISSCC 2011
@@ Line 599: / Line 598: @@
   | work=Real World Tech
   }}</ref>
-Some information was also released at the [[Hot Chips]] conference.<ref>{{cite web
+Some information was also released at the Hot Chips conference.<ref>{{cite web
   |url         = https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/
   |title         = Itanium Poulson Update&nbsp;— Greater Parallelism, New Instruction Replay & More: Catch the details from Hotchips!
@@ Line 640: / Line 639: @@
   |url-status  = dead
   |df          = mdy-all
-}}</ref>
+}}</ref> The Poulson L3 cache size is 32&nbsp;MB and common for all cores, not divided like previously. L2 cache size is 6&nbsp;MB, 512&nbsp;I&nbsp;[[Kibibyte|KB]], 256&nbsp;D&nbsp;KB per core.<ref name="dx.doi.org">{{cite conference
-The Poulson L3 cache size is 32&nbsp;MB and common for all cores, not divided like previously. L2 cache size is 6&nbsp;MB, 512&nbsp;I&nbsp;[[Kibibyte|KB]], 256&nbsp;D&nbsp;KB per core.<ref name="dx.doi.org">{{cite conference
   | chapter=A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers
   | date=February 24, 2011
@@ Line 690: / Line 688: @@
 In April 2015, Intel, although it had not yet confirmed formal specifications, did confirm that it continued to work on the project.<ref name=kitguru>{{cite web |url=https://www.kitguru.net/components/cpu/anton-shilov/intel-still-committed-to-make-new-itanium-processors/ |title=Intel still committed to make new Itanium processors |quote=KitGuru Says: Even though it is highly likely that "Kittson" chips will be released, it does not seem that Intel and HP actually want to invest R&D money in boosting performance of IA-64 chips. As a result, it looks like the best thing "Kittson" will offer will be a 20 per cent performance improvement over current gen offerings. |last1=Shilov |first1=Anton |date=April 17, 2015 |website=kitguru.net |access-date=July 4, 2023}}</ref> Meanwhile, the aggressively multicore Xeon E7 platform displaced Itanium-based solutions in the Intel roadmap.<ref>{{cite web |url=http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html |title=Intel's new Xeon server chip pushes Itanium closer to death's door |last1=Shah |first1=Agam |date=February 19, 2014 |website=pcworld.com |publisher=PC World |access-date=January 13, 2016 |archive-date=January 26, 2016 |archive-url=https://web.archive.org/web/20160126165249/http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html |url-status=live }}</ref> Even [[Hewlett-Packard]], the main proponent and customer for Itanium, began selling [[x86]]-based [[HP Superdome|Superdome]] and [[NonStop (server computers)|NonStop]] servers, and started to treat the Itanium-based versions as legacy products.<ref>{{cite web |last1=Shilov |first1=Anton |title=HP: mission-critical servers business improves as Itanium fades away |url=https://www.kitguru.net/professional/server/anton-shilov/hp-mission-critical-servers-business-improves-as-itanium-fades-away/ |website=Kitguru |access-date=30 March 2022}}</ref><ref>{{cite web |last1=Shah |first1=Agam |title=HP sees HP-UX sticking around for 10 years |url=https://www.computerworld.com/article/2853998/hp-sees-hp-ux-sticking-around-for-10-years.html |website=[[Computerworld]] |date=2 December 2014 |access-date=30 March 2022}}</ref>
-Intel officially launched the '''Itanium 9700''' series processor family on May 11, 2017.<ref>{{cite web|title=Intel® Itanium® Processor|url=https://www-ssl.intel.com/content/www/us/en/products/processors/itanium.html|website=Intel|access-date=May 15, 2017}}</ref><ref name="IA-PCWorld"/> Kittson has no microarchitecture improvements over Poulson; despite nominally having a different stepping, it is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133&nbsp;MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively.<ref>{{cite web |title=Intel® Itanium® Processor 9300, 9500 and 9700 Series Specification Update |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20201111234308/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |archive-date=11 November 2020 |url-status=live}}</ref><ref>{{cite news|last1=Cutress|first1=Ian|title=Intel's Itanium Takes One Last Breath: Itanium 9700 Series CPUs Released|url=http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|access-date=May 11, 2017|publisher=Anandtech|date=May 11, 2017|archive-date=May 11, 2017|archive-url=https://web.archive.org/web/20170511152533/http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|url-status=live}}</ref>
+Intel officially launched the '''Itanium 9700''' series processor family on May 11, 2017.<ref>{{cite web|title=Intel® Itanium® Processor|url=https://www-ssl.intel.com/content/www/us/en/products/processors/itanium.html|website=Intel|access-date=May 15, 2017}}</ref><ref name="IA-PCWorld"/> Kittson has no microarchitecture improvements over Poulson; despite nominally having a different stepping, it is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133&nbsp;MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively.<ref>{{cite web |title=Intel® Itanium® Processor 9300, 9500 and 9700 Series Specification Update |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20201111234308/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |archive-date=11 November 2020 |url-status=live}}</ref><ref>{{cite news|last1=Cutress|first1=Ian|title=Intel's Itanium Takes One Last Breath: Itanium 9700 Series CPUs Released|url=http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|access-date=May 11, 2017|publisher=Anandtech|date=May 11, 2017|archive-date=May 11, 2017|archive-url=https://web.archive.org/web/20170511152533/http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|url-status=dead}}</ref>
 Intel announced that the 9700 series would be the last Itanium chips produced.<ref name="Davis 2017" /><ref name="IA-PCWorld" />
@@ Line 722: / Line 720: @@
   }}</ref>
-According to [[Gartner Inc.]], the total number of Itanium servers (not processors) sold by all vendors in 2007, was about 55,000 (It is unclear whether clustered servers counted as a single server or not.). This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. [[International Data Corporation|IDC]] reports that a total of 184,000 Itanium-based systems were sold from 2001 through 2007. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% of revenue and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008.<ref>[[International Data Corporation|IDC]] World Wide Server Tracker, Q2'08</ref>
+According to [[Gartner Inc.]], the total number of Itanium servers (not processors) sold by all vendors in 2007, was about 55,000 (it is unclear whether clustered servers counted as a single server or not). This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. [[International Data Corporation|IDC]] reports that a total of 184,000 Itanium-based systems were sold from 2001 through 2007. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% of revenue and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008.<ref>[[International Data Corporation|IDC]] World Wide Server Tracker, Q2'08</ref>
 According to an IDC analyst, in 2007, HP accounted for perhaps 80% of Itanium systems revenue.<ref name="CW1"/>
 According to Gartner, in 2008, HP accounted for 95% of Itanium sales.<ref name="vance late"/> HP's Itanium system sales were at an annual rate of $4.4Bn at the end of 2008, and declined to $3.5Bn by the end of 2009,<ref name="Gartner 2009-q4">{{cite news
@@ Line 796: / Line 794: @@
   }}</ref>
-By 2015, only HP supplied Itanium-based systems.<ref name=kitguru/> When HP split in late 2015, Itanium systems (branded as [[HPE Integrity Servers|Integrity]])<ref name="eol">{{Cite web |last=Aleksandar |first=Kostovic |date=2021-07-31 |title=Itanium Waves Goodbye As Intel Delivers Last Shipments of Now Forgotten Processor Family |url=https://www.tomshardware.com/news/last-itanium-shipment |access-date=2022-11-29 |website=Tom's Hardware |language=en}}</ref> were handled by [[Hewlett Packard Enterprise]] (HPE), with a major update in 2017 (Integrity i6, and HP-UX 11i v3 Update 16). HPE also supports a few other operating systems, including [[Windows]] up to Server 2008 R2, [[Linux]], [[OpenVMS]] and [[NonStop (server computers)|NonStop]]. Itanium is not affected by [[Spectre (security vulnerability)|Spectre]] or [[Meltdown (security vulnerability)|Meltdown]].<ref>{{Cite news|url=https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|title=Not Vulnerable - Intel Itanium/Secure64 SourceT - Secure 64|date=January 9, 2018|work=Secure 64|access-date=October 4, 2018|language=en-US|archive-date=October 4, 2018|archive-url=https://web.archive.org/web/20181004103818/https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|url-status=live}}</ref>
+By 2015, only HP supplied Itanium-based systems.<ref name=kitguru/> When HP split in late 2015, Itanium systems (branded as [[HPE Integrity Servers|Integrity]])<ref name="eol">{{Cite web |last=Aleksandar |first=Kostovic |date=2021-07-31 |title=Itanium Waves Goodbye As Intel Delivers Last Shipments of Now Forgotten Processor Family |url=https://www.tomshardware.com/news/last-itanium-shipment |access-date=2022-11-29 |website=Tom's Hardware |language=en}}</ref> were handled by [[Hewlett Packard Enterprise]] (HPE), with a major update in 2017 (Integrity i6, and HP-UX 11i v3 Update 16). HPE also supports a few other operating systems, including [[Windows]] up to Server 2008 R2, [[Linux]], [[OpenVMS]] and [[NonStop (server computers)|Tandem NonStop]]. Itanium is not affected by [[Spectre (security vulnerability)|Spectre]] or [[Meltdown (security vulnerability)|Meltdown]] security vulnerabilities.<ref>{{Cite news|url=https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|title=Not Vulnerable - Intel Itanium/Secure64 SourceT - Secure 64|date=January 9, 2018|work=Secure 64|access-date=October 4, 2018|language=en-US|archive-date=October 4, 2018|archive-url=https://web.archive.org/web/20181004103818/https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/|url-status=live}}</ref>
 === Chipsets ===
@@ Line 819: / Line 817: @@
 The first generation of Itanium received no vendor-specific chipsets, only Intel's 460GX consisting of ten distinct chips. It supported up to four CPUs and 64 GB of memory at 4.2 GB/s, which is twice the system bus's bandwidth. Addresses and data were handled by two different chips. 460GX had an [[Accelerated Graphics Port|AGP]] X4 graphics bus, two 64-bit 66&nbsp;MHz [[Peripheral Component Interconnect|PCI]] buses and configurable 33&nbsp;MHz dual 32-bit or single 64-bit PCI bus(es).<ref>{{cite web |title=Intel 460GX Chipset Datasheet |url=http://developer.intel.com/design/itanium/downloads/24870301.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040723073549/http://developer.intel.com/design/itanium/downloads/24870301.pdf |archive-date=23 July 2004 |url-status=dead}}</ref>
-There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E8870 chipset. It supports 128 GB of [[DDR SDRAM]] at 6.4 GB/s. It was originally designed for [[Rambus]] [[RDRAM]] [[serial communication|serial]] memory, but when RDRAM failed, Intel added four DDR SDRAM-to-RDRAM converter chips to the chipset.<ref>{{cite book |last1=Mueller |first1=Scott |last2=Soper |first2=Mark Edward |last3=Sosinsky |first3=Barrie |title=Upgrading and Repairing Servers |date=2006 |publisher=Pearson Education |isbn=0-13-279698-8 |url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT301 |access-date=6 April 2022}}</ref> When Intel had previously made such a converter for Pentium III chipsets 820 and 840, it drastically cut performance.<ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Intel's 820 Chipset - Performance using SDRAM |url=https://www.anandtech.com/show/465 |website=[[AnandTech]] |access-date=6 April 2022}}</ref><ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Rambus DRAM Part 2: Performance |url=https://www.anandtech.com/show/551 |website=[[AnandTech]] |access-date=6 April 2022}}</ref> E8870 provides eight 133&nbsp;MHz [[PCI-X]] buses (4.2 GB/s total because of bottlenecks) and a [[I/O Controller Hub#ICH4|ICH4]] hub with six [[USB 2.0]] ports.
+There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E8870 chipset. It supports 128 GB of [[DDR SDRAM]] at 6.4 GB/s. It was originally designed for [[Rambus]] [[RDRAM]] [[serial communication|serial]] memory, but when RDRAM failed, Intel added four DDR SDRAM-to-RDRAM converter chips to the chipset.<ref>{{cite book |last1=Mueller |first1=Scott |last2=Soper |first2=Mark Edward |last3=Sosinsky |first3=Barrie |title=Upgrading and Repairing Servers |date=2006 |publisher=Pearson Education |isbn=0-13-279698-8 |url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT301 |access-date=6 April 2022}}</ref> When Intel had previously made such a converter for Pentium III chipsets 820 and 840, it drastically cut performance.<ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Intel's 820 Chipset - Performance using SDRAM |url=https://www.anandtech.com/show/465 |archive-url=https://web.archive.org/web/20110729150352/http://www.anandtech.com/show/465 |url-status=dead |archive-date=July 29, 2011 |website=[[AnandTech]] |access-date=6 April 2022}}</ref><ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Rambus DRAM Part 2: Performance |url=https://www.anandtech.com/show/551 |archive-url=https://web.archive.org/web/20110419010747/http://www.anandtech.com/show/551 |url-status=dead |archive-date=April 19, 2011 |website=[[AnandTech]] |access-date=6 April 2022}}</ref> E8870 provides eight 133&nbsp;MHz [[PCI-X]] buses (4.2 GB/s total because of bottlenecks) and a [[I/O Controller Hub#ICH4|ICH4]] hub with six [[USB 2.0]] ports.
-Two E8870 can be linked together by two E8870SP Scalability Port Switches, each containing a 1MB (~200,000 cache lines) [[Bus snooping#Snoop filter|snoop filter]], to create an 8-socket system with double the memory and PCI-X capacity, but still only one ICH4. Further expansion to 16 sockets was planned.<ref>{{cite journal |display-authors=etal |last=Briggs |first=Fayé |title=Intel 870: a building block for cost-effective, scalable servers |journal=[[IEEE Micro]] |date=7 August 2002 |volume=22 |issue=2 (March–April) |pages=36–47 |doi=10.1109/MM.2002.997878 |citeseerx=10.1.1.140.2915 |s2cid=3201355 }}</ref><ref>{{cite web |title=Intel® E8870 Scalable Node Controller (SNC) Datasheet |url=http://www.intel.com/design/chipsets/datashts/25111203.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040701014149/http://www.intel.com/design/chipsets/datashts/25111203.pdf |archive-date=1 July 2004 |url-status=dead}}</ref><ref>{{cite web |title=Intel® E8870IO Server I/O Hub (SIOH) Datasheet |url=http://intel.com/design/chipsets/datashts/25111103.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20030706004227/http://intel.com/design/chipsets/datashts/25111103.pdf |archive-date=6 July 2003 |url-status=dead}}</ref> In 2004 Intel revealed plans for its next Itanium chipset, codenamed ''Bayshore'', to support [[PCI-e]] and [[DDR2 SDRAM|DDR2]] memory, but canceled it the same year.<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel |access-date=7 April 2022}}</ref><ref name="ibm_ditching_itanium"/>
+Two E8870 can be linked together by two E8870SP Scalability Port Switches, each containing a 1MB (~200,000 cache lines) [[Bus snooping#Snoop filter|snoop filter]], to create an 8-socket system with double the memory and PCI-X capacity, but still only one ICH4. Further expansion to 16 sockets was planned.<ref>{{cite journal |display-authors=etal |last=Briggs |first=Fayé |title=Intel 870: a building block for cost-effective, scalable servers |journal=[[IEEE Micro]] |date=7 August 2002 |volume=22 |issue=2 (March–April) |pages=36–47 |doi=10.1109/MM.2002.997878 |bibcode=2002IMicr..22b..36B |citeseerx=10.1.1.140.2915 |s2cid=3201355 }}</ref><ref>{{cite web |title=Intel® E8870 Scalable Node Controller (SNC) Datasheet |url=http://www.intel.com/design/chipsets/datashts/25111203.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040701014149/http://www.intel.com/design/chipsets/datashts/25111203.pdf |archive-date=1 July 2004 |url-status=dead}}</ref><ref>{{cite web |title=Intel® E8870IO Server I/O Hub (SIOH) Datasheet |url=http://intel.com/design/chipsets/datashts/25111103.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20030706004227/http://intel.com/design/chipsets/datashts/25111103.pdf |archive-date=6 July 2003 |url-status=dead}}</ref> In 2004 Intel revealed plans for its next Itanium chipset, codenamed ''Bayshore'', to support [[PCI-e]] and [[DDR2 SDRAM|DDR2]] memory, but canceled it the same year.<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel |access-date=7 April 2022}}</ref><ref name="ibm_ditching_itanium"/>
 ==== Hewlett-Packard ====
@@ Line 840: / Line 838: @@
 === Unix ===
-* [[HP-UX]] 11 (supported until 2025)
+* [[HP-UX]] 11 (out of standard support; Mature Support on [[HPE Integrity]] through at least 2028<ref>{{Cite web |title=HP-UX support matrix |url=https://www.hpe.com/psnow/doc/4aa4-7673enw |quote=HPE Integrity: standard support through 31-Dec-20255 Mature Software Product Support without Sustaining Engineering through at least 31-Dec-2028}}</ref><!-- AI answer: Mature Support: Available until December 31, 2028, but offers no new fixes, acting as a limited hospice, not a production strategy, notes SUSE and SAP -->)
 === BSD ===
-* [[NetBSD]] (a tier II port<ref>{{Cite web|title=Platforms Supported by NetBSD|url=https://www.netbsd.org/ports/|access-date=2021-03-02|website=www.netbsd.org|archive-date=2021-02-27|archive-url=https://web.archive.org/web/20210227091416/http://www.netbsd.org/ports/|url-status=live}}</ref> that "is a work-in-progress effort to port NetBSD to the Itanium family of processors. Currently no formal release is available."<ref>{{Cite web|title=NetBSD/ia64|url=http://wiki.netbsd.org/ports/ia64/|access-date=2021-03-02|website=wiki.netbsd.org|archive-date=2018-04-27|archive-url=https://web.archive.org/web/20180427122809/http://wiki.netbsd.org/ports/ia64/|url-status=live}}</ref>)
+* [[NetBSD]] (currently has no support;<!-- "none" under a tier II port --><ref>{{Cite web|title=Platforms Supported by NetBSD|url=https://www.netbsd.org/ports/|access-date=2025-12-31|website=www.netbsd.org|archive-date=2021-02-27|archive-url=https://web.archive.org/web/20210227091416/http://www.netbsd.org/ports/|url-status=live}}</ref> likely outdated page states "is a work-in-progress effort to port NetBSD to the Itanium family of processors. Currently no formal release is available."<ref>{{Cite web|title=NetBSD/ia64|url=http://wiki.netbsd.org/ports/ia64/|access-date=2021-03-02|website=wiki.netbsd.org|archive-date=2018-04-27|archive-url=https://web.archive.org/web/20180427122809/http://wiki.netbsd.org/ports/ia64/|url-status=live}}</ref>)
 *[[FreeBSD]] (unsupported since 31 October 2018)
@@ Line 849: / Line 847: @@
 The Trillian Project was an effort by an industry consortium to port the [[Linux]] kernel to the Itanium processor. The project started in May 1999 with the goal of releasing the distribution in time for the initial release of Itanium, then scheduled for early 2000.<ref name="Sabbagh">{{cite web|last=Sabbagh|first=Dan|date=3 Feb 2000|title=Trillian releases Linux code for Itanium|url=http://www.vnunet.com/vnunet/news/2111194/trillian-releases-linux-code-itanium|archive-url=https://web.archive.org/web/20070930200218/http://www.vnunet.com/vnunet/news/2111194/trillian-releases-linux-code-itanium|archive-date=30 September 2007|url-status=dead|access-date=2007-03-20|work=vnunet.com}}</ref> By the end of 1999, the project included [[Caldera Systems]], [[CERN]], [[Cygnus Solutions]], [[Hewlett-Packard]], [[IBM]], [[Intel]], [[Red Hat]], [[Silicon Graphics|SGI]], [[SUSE S.A.|SuSE]], [[TurboLinux]] and [[VA Linux Systems]].<ref>{{cite press release|date=December 20, 1999|title=Leading Linux Distributors Join the Trillian Project|url=https://www.redhat.com/en/about/press-releases/press-trillian|access-date=2007-03-20|website=Red Hat}}</ref> The project released the resulting code in February 2000.<ref name="Sabbagh" /> The code then became part of the [[mainline Linux kernel]] more than a year before the release of the first Itanium processor. The Trillian project was able to do this for two reasons:
-* the [[Free software|free]] and [[Open source software|open source]] [[GNU Compiler Collection|GCC]] compiler had already been enhanced to support the Itanium architecture.
+* the [[Free software|free]] and [[Open source software|open source]] [[GNU Compiler Collection|GCC]] compiler had already been enhanced to support the Itanium architecture.<ref>{{Cite web |title=Did you know Origins were gonna have Merced? |url=https://forums.irixnet.org/thread-4714-post-34921.html#pid34921 |access-date=2025-11-11 |website=forums.irixnet.org}}</ref><ref>{{Cite web |title=GCC 4.2 Release Series — Changes, New Features, and Fixes - GNU Project |url=https://gcc.gnu.org/gcc-4.2/changes.html |access-date=2025-11-11 |website=gcc.gnu.org}}</ref>
 * a free and open source simulator had been developed to simulate an Itanium processor on an existing computer.<ref>{{cite web| url = http://www.irisa.fr/caps/projects/ArchiCompil/iato/| title = IATO simulation environment}}</ref>
@@ Line 855: / Line 853: @@
 ==== Distribution support ====
-In 2005, Fedora Linux started adding support for Itanium<ref>{{Cite web|last=Shankland|first=Stephen|title=Fedora for Itanium taking baby steps|url=https://www.cnet.com/culture/fedora-for-itanium-taking-baby-steps/|access-date=2023-07-04|website=CNET|date=22 March 2005 |language=en}}</ref> and Novell added support for SUSE Linux.<ref>{{Cite web|last=Connor|first=Deni|date=2005-01-06|title=Novell releases SuSE Linux for HP Itanium servers|url=https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|access-date=2021-10-14|website=Network World|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029172431/https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|url-status=live}}</ref> In 2007, [[CentOS]] added support for Itanium in a new release.<ref>{{Cite web|title=CentOS 5 Linux released|url=https://www.itpro.co.uk/110119/centos-5-linux-released|access-date=2021-10-14|website=IT PRO|date=14 April 2007 |language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029170900/https://www.itpro.co.uk/110119/centos-5-linux-released|url-status=live}}</ref>
+In 2003, Debian 3.0 (Woody) had support for Itanium<ref>{{cite web |last1=Debian |title=Release Notes for Debian GNU/Linux 3.0 (`woody'), IA-64 |url=https://www.debian.org/releases/woody/ia64/release-notes.en.txt |website=debian |publisher=Software in the Public Interest, Inc. |access-date=11 February 2026}}</ref>. In 2005, Fedora Linux started adding support for Itanium<ref>{{Cite web|last=Shankland|first=Stephen|title=Fedora for Itanium taking baby steps|url=https://www.cnet.com/culture/fedora-for-itanium-taking-baby-steps/|access-date=2023-07-04|website=CNET|date=22 March 2005 |language=en}}</ref> and Novell added support for SUSE Linux.<ref>{{Cite web|last=Connor|first=Deni|date=2005-01-06|title=Novell releases SuSE Linux for HP Itanium servers|url=https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|access-date=2021-10-14|website=Network World|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029172431/https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html|url-status=live}}</ref> In 2007, [[CentOS]] added support for Itanium in a new release.<ref>{{Cite web|title=CentOS 5 Linux released|url=https://www.itpro.co.uk/110119/centos-5-linux-released|access-date=2021-10-14|website=IT PRO|date=14 April 2007 |language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029170900/https://www.itpro.co.uk/110119/centos-5-linux-released|url-status=live}}</ref>
 * [[Debian]] (official support was dropped in Debian 8; unofficial support available through Debian Ports until June 2024<ref>{{cite web|title=Debian Ports|url=https://www.ports.debian.org|access-date=2024-10-27}}</ref>)
@@ Line 866: / Line 864: @@
 ==== Deprecation ====
-In 2009, Red Hat dropped Itanium support in Enterprise Linux 6.<ref name="red-hat-to-drop-itanium">{{Cite web|last=Ricknäs|first=Mikael|date=2009-12-21|title=Red Hat to drop Itanium support in Enterprise Linux 6|url=https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|access-date=2021-10-14|website=[[Computerworld]]|language=en|archive-date=2021-10-28|archive-url=https://web.archive.org/web/20211028172143/https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|url-status=live}}</ref> Ubuntu 10.10 dropped support for Itanium.<ref>{{Cite web|last=Clark|first=Jack|title=SPARC and Itanium support discontinued in Ubuntu 10.10|url=https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|access-date=2021-10-14|website=ZDNet|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029180056/https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|url-status=live}}</ref> In 2021, Linus Torvalds marked the Itanium code as orphaned. Torvalds said:
+In 2009, Red Hat dropped Itanium support in Enterprise Linux 6.<ref name="red-hat-to-drop-itanium">{{Cite web|last=Ricknäs|first=Mikael|date=2009-12-21|title=Red Hat to drop Itanium support in Enterprise Linux 6|url=https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|access-date=2021-10-14|website=[[Computerworld]]|language=en|archive-date=2021-10-28|archive-url=https://web.archive.org/web/20211028172143/https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html|url-status=live}}</ref> Ubuntu 10.10 dropped support for Itanium.<ref>{{Cite web|last=Clark|first=Jack|title=SPARC and Itanium support discontinued in Ubuntu 10.10|url=https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|access-date=2021-10-14|website=ZDNet|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029180056/https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/|url-status=live}}</ref> In 2021, Linus Torvalds marked the Itanium code as orphaned. Torvalds said: "HPE no longer accepts orders for new Itanium hardware, and Intel stopped accepting orders a year ago. While intel{{Sic}} is still officially shipping chips until July 29, 2021, it's unlikely that any such orders actually exist. [[He's dead, Jim|It's dead, Jim]]."<ref>{{Cite news|first=Tim|last=Anderson|title='It's dead, Jim': Torvalds marks Intel Itanium processors as orphaned in Linux kernel|url=https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|access-date=2021-10-14|work=[[The Register]]|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029174912/https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|url-status=live}}</ref><ref>{{Cite web|title=kernel/git/torvalds/linux.git - Linux kernel source tree|url=https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|access-date=2021-10-14|website=[[kernel.org]]|archive-date=2021-11-03|archive-url=https://web.archive.org/web/20211103183816/https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|url-status=live}}</ref>
-"HPE no longer accepts orders for new Itanium hardware, and Intel stopped accepting orders a year ago. While intel is still officially shipping chips until July 29, 2021, it's unlikely that any such orders actually exist. [[He's dead, Jim|It's dead, Jim]]."<ref>{{Cite news|first=Tim|last=Anderson|title='It's dead, Jim': Torvalds marks Intel Itanium processors as orphaned in Linux kernel|url=https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|access-date=2021-10-14|work=[[The Register]]|language=en|archive-date=2021-10-29|archive-url=https://web.archive.org/web/20211029174912/https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/|url-status=live}}</ref><ref>{{Cite web|title=kernel/git/torvalds/linux.git - Linux kernel source tree|url=https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|access-date=2021-10-14|website=[[kernel.org]]|archive-date=2021-11-03|archive-url=https://web.archive.org/web/20211103183816/https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a|url-status=live}}</ref>
 Support for Itanium was removed in Linux 6.7<ref>{{Cite web |title=kernel/git/next/linux-next.git - The linux-next integration testing tree |url=https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=cf8e8658100d4eae80ce9b21f7a81cb024dd5057 |access-date=2023-09-18 |website=git.kernel.org}}</ref><ref>{{Cite web |title=Linux 6.7 Set To Drop Support For Itanium IA-64 |url=https://www.phoronix.com/news/Linux-6.7-To-Drop-Itanium-IA-64 |access-date=2023-09-18 |website=www.phoronix.com |language=en}}</ref> and is since then maintained [[wiktionary:out-of-tree|out-of-tree]].<ref>{{cite web |url=https://github.com/linux-ia64/ |title=linux-ia64 |website=GitHub |quote=Maintenance and development of the Linux operating system for Intel Itanium architecture (IA-64) |access-date=October 1, 2024}}</ref><ref>{{cite web |url=http://epic-linux.org/ |title=EPIC Linux |access-date=October 1, 2024}}</ref>
@@ Line 893: / Line 889: @@
 === NonStop OS ===
-[[NonStop OS]] was ported from [[MIPS architecture|MIPS]]-based hardware to Itanium in 2005.<ref>{{cite web|url=https://www.hpe.com/psnow/doc/4AA0-6149ENW|title=HPE NonStop OS|date=April 2018|publisher=HPE|access-date=2021-11-22|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122135935/https://www.hpe.com/psnow/doc/4AA0-6149ENW|url-status=live}}</ref> NonStop OS was later ported to x86-64 in 2015. Sales of Itanium-based NonStop hardware ended in 2020, with support ending in 2025.<ref name="hpe-brochure">{{cite web|url=https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|title=HPE NonStop family of systems|publisher=HPE|date=May 2021|access-date=2021-11-22|archive-date=2022-01-21|archive-url=https://web.archive.org/web/20220121201745/https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|url-status=live}}</ref><ref>{{cite web|url=https://connect2nonstop.com/2371-2/|title=News from HPE's NonStop Enterprise Division|author=Prashanth Kamath U|date=2019-07-30|access-date=2021-11-22|website=The Connection|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122140545/https://connect2nonstop.com/2371-2/|url-status=live}}</ref>
+[[NonStop OS|Tandem NonStop OS]] was ported from [[MIPS architecture|MIPS]]-based hardware to Itanium in 2005.<ref>{{cite web|url=https://www.hpe.com/psnow/doc/4AA0-6149ENW|title=HPE NonStop OS|date=April 2018|publisher=HPE|access-date=2021-11-22|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122135935/https://www.hpe.com/psnow/doc/4AA0-6149ENW|url-status=live}}</ref> NonStop OS was later ported to x86-64 in 2015. Sales of Itanium-based NonStop hardware ended in 2020, with support ending in 2025.<ref name="hpe-brochure">{{cite web|url=https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|title=HPE NonStop family of systems|publisher=HPE|date=May 2021|access-date=2021-11-22|archive-date=2022-01-21|archive-url=https://web.archive.org/web/20220121201745/https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf|url-status=live}}</ref><ref>{{cite web|url=https://connect2nonstop.com/2371-2/|title=News from HPE's NonStop Enterprise Division|author=Prashanth Kamath U|date=2019-07-30|access-date=2021-11-22|website=The Connection|archive-date=2021-11-22|archive-url=https://web.archive.org/web/20211122140545/https://connect2nonstop.com/2371-2/|url-status=live}}</ref>
 === Compiler ===
 [[GNU Compiler Collection]] deprecated support for IA-64 in GCC 10, after Intel announced the planned phase-out of this ISA.<ref>{{cite web |title=Intel Itanium IA-64 Support To Be Deprecated By GCC 10, Planned Removal In GCC 11 |url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-IA-64-GCC-Deprecation |website=Phoronix |access-date=2020-07-09 |archive-date=2020-07-11 |archive-url=https://web.archive.org/web/20200711001829/https://www.phoronix.com/scan.php?page=news_item&px=Intel-IA-64-GCC-Deprecation |url-status=live }}</ref> [[LLVM]] (Clang) dropped Itanium support in version 2.6.<ref>{{Cite web|date=Jul 24, 2009|title=Remove the IA-64 backend. · llvm/llvm-project@1715115 · GitHub|url=https://github.com/llvm/llvm-project/commit/17151155ed8f83dcbb5db69bca2839ac2da19e0e|website=GitHub}}</ref>
+However, Itanium's C++ ABI continues to be the ABI used for both GCC and LLVM on most CPU architectures.<ref>{{Cite web |title=ABI Policy and Guidelines |url=https://gcc.gnu.org/onlinedocs/libstdc++/manual/abi.html |access-date=2025-11-11 |website=gcc.gnu.org}}</ref>
 === Virtualization and emulation ===
@@ Line 1,042: / Line 1,040: @@
   | access-date=November 25, 2022
   }}</ref>
-Itanium failed to make significant inroads against [[IA-32]] or RISC, and suffered further following the arrival of [[x86-64]] systems which offered greater compatibility with older x86 applications.
+Itanium failed to make significant inroads against [[IA-32]] or RISC, and suffered further following the arrival of [[x86-64]] systems which offered complete compatibility with older x86 applications at full, native performance without emulation.
 In a 2009 article on the history of the processor — "How the Itanium Killed the Computer Industry" — journalist [[John C. Dvorak]] reported "This continues to be one of the great fiascos of the last 50 years".<ref>{{cite web
@@ Line 1,158: / Line 1,156: @@
 {{Intel processors}}
 {{CPU technologies}}
+{{Hewlett-Packard}}
 {{Authority control}}
@@ Line 1,167: / Line 1,165: @@
 [[Category:VLIW microprocessors]]
 [[Category:Products and services discontinued in 2021]]
+[[Category:HP microprocessors]]

Itanium: Difference between revisions

Navigation menu

Search