Control store: Difference between revisions
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imported>Guy Harris →Writable stores: More clearly explain what appears to have been meant by the text about the Recursiv processor and the Imsys Cjip, namely that different microcode implements different instruction sets for different programming languages, Add the Burroughs Small Systems to that list. Remove the bit about FPGAs, as that's reprogrammable logic rather than reprogrammable microcode. |
imported>SchlurcherBot m Bot: http → https |
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A '''control store''' is the part of a [[ | A '''control store''' is the part of a [[CPU]]'s [[control unit]] that stores the CPU's [[microprogram]]. It is usually accessed by a [[microsequencer]]. A control store implementation whose contents are unalterable is known as a [[read-only memory]] (ROM) or Read Only Storage (ROS); one whose contents are alterable is known as a Writable Control Store (WCS). | ||
<!-- WCS is not a form of ROM --> | <!-- WCS is not a form of ROM --> | ||
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===Writable stores=== | ===Writable stores=== | ||
Some computers are built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''Writable Instruction Set Computer'' or ''WISC''.<ref>{{cite journal | url = | Some computers are built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''Writable Instruction Set Computer'' or ''WISC''.<ref>{{cite journal | url = https://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf | title = Writable instruction set, stack oriented computers: The WISC Concept | journal = The Journal of Forth Application and Research | volume = 5 | issue = 1 | pages=49–71 | first = Philip | last = Koopman Jr. | date = 1987}}</ref> Many of these machines were experimental laboratory prototypes, such as the WISC CPU/16<ref>{{cite book | chapter-url = https://users.ece.cmu.edu/~koopman/stack_computers/sec4_2.html | chapter = Architecture of the WISC CPU/16 | title = Stack Computers: the new wave | url = https://users.ece.cmu.edu/~koopman/stack_computers/index.html | first = Philip | last = Koopman Jr. | date = 1989}}</ref> and the RTX 32P.<ref>{{cite book | chapter-url = https://users.ece.cmu.edu/~koopman/stack_computers/sec5_3.html | chapter = Architecture of the RTX 32P | title = Stack Computers: the new wave | url = https://users.ece.cmu.edu/~koopman/stack_computers/index.html | first = Philip | last = Koopman Jr. | date = 1989}}</ref> | ||
The original [[IBM System/360|System/360]] models have read-only control store, but later System/360, [[IBM System/370|System/370]] and successor models load part or all of their microprograms from floppy disks or other [[Direct access storage device|DASD]] into a writable control store consisting of ultra-high speed [[random-access memory|random-access]] [[read–write memory]]. The System/370 architecture includes a facility called '''Initial-Microprogram Load''' ('''IML''' or '''IMPL''')<ref>{{cite manual | The original [[IBM System/360|System/360]] models have read-only control store, but later System/360, [[IBM System/370|System/370]] and successor models load part or all of their microprograms from floppy disks or other [[Direct access storage device|DASD]] into a writable control store consisting of ultra-high speed [[random-access memory|random-access]] [[read–write memory]]. The System/370 architecture includes a facility called '''Initial-Microprogram Load''' ('''IML''' or '''IMPL''')<ref>{{cite manual | ||
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| version = Fourth Edition | | version = Fourth Edition | ||
| date = September 1974 | | date = September 1974 | ||
| url = | | url = https://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf | ||
| pages = 98, 245 | | pages = 98, 245 | ||
|mode=cs2 | |mode=cs2 | ||
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| title = IBM System/360 Model 85 Functional Characteristics | | title = IBM System/360 Model 85 Functional Characteristics | ||
| id = A22-6916-1 | | id = A22-6916-1 | ||
| url = | | url = https://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6916-1_360-85_funcChar_Jun68.pdf | ||
| version = SECOND EDITION | | version = SECOND EDITION | ||
| date = June 1968 | | date = June 1968 | ||
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| title = IBM System/370 Model 155 Functional Characteristics | | title = IBM System/370 Model 155 Functional Characteristics | ||
| id = GA22-6942-1 | | id = GA22-6942-1 | ||
| url = | | url = https://www.bitsavers.org/pdf/ibm/370/funcChar/GA22-6942-1_370-155_funcChar_Jan71.pdf | ||
| version = SECOND EDITION | | version = SECOND EDITION | ||
| date = January 1971 | | date = January 1971 | ||
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Other commercial machines that use writable microcode include the [[Burroughs Small Systems]] (1970s and 1980s), the Xerox processors in their [[Lisp machine]]s and [[Xerox Star]] workstations, the [[Digital Equipment Corporation|DEC]] [[VAX]] 8800 ("Nautilus") family, and the [[Symbolics]] L- and G-machines (1980s). Some DEC [[PDP-10]] machines store their microcode in SRAM chips (about 80 bits wide x 2 Kwords), which is typically loaded on power-on through some other front-end CPU.<ref>{{Cite newsgroup|url=http://pdp10.nocrew.org/cpu/kl10-ucode.txt|title=Re: What was the size of Microcode in various machines|first=Eric|last=Smith|newsgroup=comp.arch|date=September 3, 2002}}</ref> Many more machines offer user-programmable writable control stores as an option (including the [[HP 2100]], DEC [[PDP-11|PDP-11/60]] and [[Varian Data Machines]] V-70 series [[minicomputer]]s). | Other commercial machines that use writable microcode include the [[Burroughs Small Systems]] (1970s and 1980s), the Xerox processors in their [[Lisp machine]]s and [[Xerox Star]] workstations, the [[Digital Equipment Corporation|DEC]] [[VAX]] 8800 ("Nautilus") family, and the [[Symbolics]] L- and G-machines (1980s). Some DEC [[PDP-10]] machines store their microcode in SRAM chips (about 80 bits wide x 2 Kwords), which is typically loaded on power-on through some other front-end CPU.<ref>{{Cite newsgroup|url=http://pdp10.nocrew.org/cpu/kl10-ucode.txt|title=Re: What was the size of Microcode in various machines|first=Eric|last=Smith|newsgroup=comp.arch|date=September 3, 2002}}</ref> Many more machines offer user-programmable writable control stores as an option (including the [[HP 2100]], DEC [[PDP-11|PDP-11/60]] and [[Varian Data Machines]] V-70 series [[minicomputer]]s). | ||
The [[Mentec PDP-11#M11|Mentec M11]] and [[Mentec PDP-11#M1|Mentec M1]] store its microcode in SRAM chips, loaded on power-on through another CPU. | The [[Mentec PDP-11#M11|Mentec M11]] and [[Mentec PDP-11#M1|Mentec M1]] store its microcode in SRAM chips, loaded on power-on through another CPU. | ||
The [[Data General Eclipse MV/8000]] ("Eagle") has a SRAM writable control store, loaded on power-on through another CPU.<ref>{{cite web|author=Mark Smotherman|title=CPSC 330 / The Soul of a New Machine|url= | The [[Data General Eclipse MV/8000]] ("Eagle") has a SRAM writable control store, loaded on power-on through another CPU.<ref>{{cite web|author=Mark Smotherman|title=CPSC 330 / The Soul of a New Machine|url=https://www.cs.clemson.edu/~mark/330/eagle.html|quote=4096 x 75-bit SRAM writeable control store: 74-bit microinstruction with 1 parity bit (18 fields)}}</ref> | ||
WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs could provide. User-programmable WCS allow the user to optimize the machine for specific purposes. However, it also had the disadvantage of making it harder to debug programs, and making it possible for malicious users to negatively affect the system and data.<ref>{{cite journal |last=McDowell |first=Charlie |date=1982 |title=Protection at the micromachine level |url=https://dl.acm.org/doi/pdf/10.1145/859520.859521 |journal=ACM SIGARCH Computer Architecture News |volume=10 |issue=1 |pages=5 |doi=10.1145/859520.859521 |access-date=2023-11-25 |quote=It is not unusual to find microprograms that are greater than 50K bytes in size. This increase in size, and the expansion of microprograming beyond the traditional bounds of machine instruction emulation, have increased the possibility of both malicious and faulty microprograms, particularly the later.|url-access=subscription }}</ref> | WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs could provide. User-programmable WCS allow the user to optimize the machine for specific purposes. However, it also had the disadvantage of making it harder to debug programs, and making it possible for malicious users to negatively affect the system and data.<ref>{{cite journal |last=McDowell |first=Charlie |date=1982 |title=Protection at the micromachine level |url=https://dl.acm.org/doi/pdf/10.1145/859520.859521 |journal=ACM SIGARCH Computer Architecture News |volume=10 |issue=1 |pages=5 |doi=10.1145/859520.859521 |access-date=2023-11-25 |quote=It is not unusual to find microprograms that are greater than 50K bytes in size. This increase in size, and the expansion of microprograming beyond the traditional bounds of machine instruction emulation, have increased the possibility of both malicious and faulty microprograms, particularly the later.|url-access=subscription }}</ref> | ||
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==Further reading== | ==Further reading== | ||
* {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=1 |url= | * {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=1 |url=https://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_1_Sep47.pdf |access-date=2021-11-12 |url-status=live |archive-url=https://web.archive.org/web/20210815014917/http://bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_1_Sep47.pdf |archive-date=2021-08-15}} (132 pages) | ||
* {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=2 |url= | * {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=2 |url=https://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_2_Sep47.pdf |access-date=2021-11-12 |url-status=live |archive-url=https://web.archive.org/web/20210815015419/http://bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_2_Sep47.pdf |archive-date=2021-08-15}} (79 pages) | ||
* {{cite journal |author-last=Smith |author-first=Richard E. |title=A Historical Overview of Computer Architecture |journal=[[Annals of the History of Computing]] |publisher=[[IEEE]] |date=October–December 1988 |volume=10 |issue=4 |pages=277–303 |doi=10.1109/MAHC.1988.10039 |s2cid=16405547 |url= | * {{cite journal |author-last=Smith |author-first=Richard E. |title=A Historical Overview of Computer Architecture |journal=[[Annals of the History of Computing]] |publisher=[[IEEE]] |date=October–December 1988 |volume=10 |issue=4 |pages=277–303 |doi=10.1109/MAHC.1988.10039 |s2cid=16405547 |url=https://doi.ieeecomputersociety.org/10.1109/MAHC.1988.10039 |access-date=2006-06-21|url-access=subscription }} | ||
{{wikibooks | {{wikibooks | ||
|1= Microprocessor Design | |1= Microprocessor Design | ||